I implement a one to two clock buffer in my design and feed to two different pins of a module. I need to have two distinct clock names so that we can control max/min delay between them in my timing constrain. I did the following:
out1 = inclock;
out2 = inclock;
However, the get_clocks command in timing constrain cannot match out1 and out2 with a clock. It looks like the tool see out1 and out2 as io signals, not clock. Do I need to do anything special to out1 and out2 so that the get_clocks command can recognize them as clock and applies the constrains.
Time Quest will not recognise out1 or out2 as clocks unless they feed a design element that is clocked - such as a flip-flop or PLL.
If you need to analyse the delay out then you'll need a set_output_delay command. However, I get the impression you're trying to control the delay out using timing constraints. Is that right? You need to do this by design, not through the use of timing constraints.
Thank you Alex. I need to set the max delay between the two clocks to 5ns by:
set_max_delay -from get_clocks out1 -to get_clocks out2 5.00
set_max_delay -from get_clocks out2 -to get_clocks out1 5.00
but the get_clocks command does not recognize out1 and out2 as clock. I understand that using PLL will work but is there any simpler implementation than PLL?
So the rising/falling edge of out2 must be within 5ns of out1? Or are you trying to design something where the edges are locked 5ns apart?
If it's the latter then you need a PLL with multiple output clocks. As I mentioned before, you need to ensure this by design. Timing constraints will only tell you whether your design meets timing.