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Altera_Forum
Honored Contributor I
1,128 Views

Issues with access to array of accesses

Hello everyone, 

 

 

I am encountering issues with exotic VHDL constructs, and I would love your help... 

 

 

 

 

 

 

I am trying to write procedures that will be useful to me when building testbenches. 

These procedures are intended to read and write text files. 

 

 

I declared 2 types:  

type t_line_vector is array (natural range <>) of line; type t_line_vector_ptr is access t_line_vector; (And as a reminder, from textio, type line is access string;

 

 

The t_line_vector_ptr is a data structure similar to the char ** argv from C. 

 

 

Then, I wrote 2 procedures: 

procedure read_file(filename : in string; line_vector_ptr : out t_line_vector_ptr); procedure write_file(line_vector_ptr : inout t_line_vector_ptr; filename : in string);  

 

These are intended respectively to load the content of a file into a t_line_vector_ptr, and to write the content of a t_line_vector_ptr into a file. 

 

 

Then wrote a testbench that reads the content of a file and writes it to another file. 

 

 

The code is attached to this post. It is pretty simple, and it compiles without warning. 

 

 

Then when I simulate it, I get nasty access errors: 

 

 

 

 

 

 

- with Modelsim Intel Starter Edition 10.5b: 

 

 

 

--- Quote Start ---  

$ vlib work 

 

 

$ vcom -work work test.vhd 

Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 

Start time: 18:52:31 on Apr 05,2017 

vcom -work work test.vhd  

-- Loading package STANDARD 

-- Loading package TEXTIO 

-- Compiling entity test 

-- Compiling architecture rtl of test 

End time: 18:52:31 on Apr 05,2017, Elapsed time: 0:00:00 

Errors: 0, Warnings: 0 

 

 

$ vsim work.test -batch -do "run -all"# vsim work.test -batch -do "run -all" # Start time: 18:52:37 on Apr 05,2017# Loading std.standard# Loading std.textio(body)# Loading work.test(rtl)# # run -all# ** Fatal: (vsim-5) ****** Memory failure. *****# Bad pointer/access type passed to memory subsystem.# Pointer may have been previously deallocated.# ** Fatal: (vsim-5) ****** Memory failure. *****# Bad pointer/access type passed to memory subsystem.# Pointer may have been previously deallocated.# ** Fatal: (vsim-5) ****** Memory failure. *****# Bad pointer/access type passed to memory subsystem.# Pointer may have been previously deallocated.# ** Fatal: (vsim-5) ****** Memory failure. *****# Bad pointer/access type passed to memory subsystem.# Pointer may have been previously deallocated.# ** Fatal: (vsim-5) ****** Memory failure. *****# Bad pointer/access type passed to memory subsystem.# Pointer may have been previously deallocated.# ** Fatal: (vsim-5) ****** Memory failure. *****# Bad pointer/access type passed to memory subsystem.# Pointer may have been previously deallocated.# ** Fatal: (vsim-5) ****** Memory failure. *****# Bad pointer/access type passed to memory subsystem.# Pointer may have been previously deallocated.# ** Fatal: (vsim-5) ****** Memory failure. *****# Bad pointer/access type passed to memory subsystem.# Pointer may have been previously deallocated.# ** Fatal: (vsim-5) ****** Memory failure. *****# Bad pointer/access type passed to memory subsystem.# Pointer may have been previously deallocated.# ** Fatal: (vsim-5) ****** Memory failure. *****# Bad pointer/access type passed to memory subsystem.# Pointer may have been previously deallocated.# ** Fatal: (vsim-5) ****** Memory failure. *****# Bad pointer/access type passed to memory subsystem.# Pointer may have been previously deallocated. 

VSIM 2># End time: 18:52:39 on Apr 05,2017, Elapsed time: 0:00:02# Errors: 11, Warnings: 0 

 

--- Quote End ---  

 

 

 

 

 

 

- I decided to try also with Vivado 2016.4, just to see, and I get: 

 

 

 

--- Quote Start ---  

$ xvhdl test.vhd 

INFO: [VRFC 10-163] Analyzing VHDL file "test.vhd" into library work 

INFO: [VRFC 10-307] analyzing entity test 

 

 

$ xelab -debug typical test -s test 

Vivado Simulator 2016.4 

Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. 

Running: /opt/Xilinx/Vivado/2016.4/bin/unwrapped/lnx64.o/xelab -debug typical test -s test  

Multi-threading is on. Using 2 slave threads. 

Starting static elaboration 

Completed static elaboration 

Starting simulation data flow analysis 

Completed simulation data flow analysis 

Time Resolution for simulation is 1ps 

Compiling package std.standard 

Compiling package std.textio 

Compiling architecture rtl of entity work.test 

Built simulation snapshot test 

 

 

****** Webtalk v2016.4 (64-bit) 

**** SW Build 1756540 on Mon Jan 23 19:11:19 MST 2017 

**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017 

** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 

 

 

source xsim.dir/test/webtalk/xsim_webtalk.tcl -notrace 

INFO: [Common 17-186] 'xsim.dir/test/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Wed Apr 5 18:54:06 2017. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2016.4/doc/webtalk_introduction.html. 

INFO: [Common 17-206] Exiting Webtalk at Wed Apr 5 18:54:06 2017... 

 

 

$ xsim test -R 

 

 

****** xsim v2016.4 (64-bit) 

**** SW Build 1756540 on Mon Jan 23 19:11:19 MST 2017 

**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017 

** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 

 

 

source xsim.dir/test/xsim_script.tcl# xsim {test} -autoloadwcfg -runall 

Vivado Simulator 2016.4 

Time resolution is 1 ps 

run -all 

ERROR: Attempting to dereference a dangling (deallocated) access value 

Time: 0 ps Iteration: 0 Process: /test/line__78 

File: test.vhd 

 

 

HDL Line: test.vhd:85 

exit 

INFO: [Common 17-206] Exiting xsim at Wed Apr 5 18:54:27 2017... 

 

--- Quote End ---  

 

 

Is there something wrong with my code? 

Or is it that both tools do not support access to array of accesses correctly? 

 

 

- Julien
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
117 Views

I can see what you're trying to do here - read the entire file into an array.  

Modelsim definitely supports arrays of access types - I have done it plenty of times. And you can put access types in records (a handy way to build linked lists). The problem will be because the readline procedure deallocates current_line before putting the new line into current_line. As you are storing current_line in the array, and not current_line.all, the data dissapears. 

 

IMHO, you're overcomplicating things here. You could just have a function called "get_file_length" to return the number of lines in the file, then create an array of that length and return the array, without having it being a pointer to an array of lines. Something like this (I prefer functions for the type of stuff you have done): 

 

function get_file_length(filename : string) return natural is variable ret : natural := 0; file f : text open read_mode is filename; variable l : line; begin while not ENDFILE(f) loop readline(f,l); ret := ret + 1; end loop; return ret; end; function read_file(filename : string) return t_line_vector is constant N_LINES : natural := get_file_length(filename); file f : text open read_mode is filename; variable res : t_line_vector(0 to N_LINES-1) variable l : line; begin for i in res'range loop readline(f, l); res(i) = new string(l'range); res(i).all = l.all; end loop; return res; end function read_file; function read_file(filename : string) return t_line_vector_ptr is variable res : t_line_vector_ptr; begin res = new t_line_vector( t_line_vector'(read_file(filename) ) ) return res; end function read_file;
Altera_Forum
Honored Contributor I
117 Views

Oh I did not know that readline() deallocates the pointer... 

Thanks a lot!
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