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Beginner
68 Views

It produced no waveform output(xx) of the state machine using d flip-flop

I was trying to stimulate the state machine with d flip-flop. There wasn’t any error while compiling. But whatever the input value I set, the University Program VWF doesn’t produced any waveform output. Please help me!!

Below is my code:

module state_machine_d(Q, Qn, C, x,y);
output Q;
output Qn;
input C;
input x;
input y;

wire w1;
wire D;
wire Cn; // Control input to the D latch.
wire Cnn; // Control input to the SR latch.
wire DQ; // Output from the D latch, input to the gated SR latch.
wire DQn; // Output from the D latch, input to the gated SR latch.

not(Cn, C);
not(Cnn, Cn);
xor(w1,x,y);
xor(D,Q,w1);
d_latch dl(DQ, DQn, Cn, D);
sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);
endmodule

module d_latch(Q, Qn, G, D);
output Q;
output Qn;
input G;
input D;

wire Dn;
wire D1;
wire Dn1;

not(Dn, D);
and(D1, G, D);
and(Dn1, G, Dn);
nor(Qn, D1, Q);
nor(Q, Dn1, Qn);
endmodule // d_latch

module sr_latch_gated(Q, Qn, G, S, R);
output Q;
output Qn;
input G;
input S;
input R;

wire S1;
wire R1;

and(S1, G, S);
and(R1, G, R);
nor(Qn, S1, Q);
nor(Q, R1, Qn);
endmodule // sr_latch_gated
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2 Replies
Highlighted
Beginner
67 Views

Oh sorry~I forgot to attach my waveform photo. Here it is.
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Highlighted
Moderator
13 Views

Hi Jun,


I would suggest you to view you RTL netlist and see the logic if they are designed as intended and the logic and connections have been interpreted correctly by the software. You can use the RTL Viewer and State Machine Viewer to check your design visually before simulation. Tool --> Netlist Viewer --> RTL viewer/state machine viewer.


Analyzing Designs with Quartus II Netlist Viewers

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51013.pdf


Thanks,

Regards


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