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It produced no waveform output(xx) of the state machine using d flip-flop

Jun-Yan-Wu
Beginner
281 Views
I was trying to stimulate the state machine with d flip-flop. There wasn’t any error while compiling. But whatever the input value I set, the University Program VWF doesn’t produced any waveform output. Please help me!!

Below is my code:

module state_machine_d(Q, Qn, C, x,y);
output Q;
output Qn;
input C;
input x;
input y;

wire w1;
wire D;
wire Cn; // Control input to the D latch.
wire Cnn; // Control input to the SR latch.
wire DQ; // Output from the D latch, input to the gated SR latch.
wire DQn; // Output from the D latch, input to the gated SR latch.

not(Cn, C);
not(Cnn, Cn);
xor(w1,x,y);
xor(D,Q,w1);
d_latch dl(DQ, DQn, Cn, D);
sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);
endmodule

module d_latch(Q, Qn, G, D);
output Q;
output Qn;
input G;
input D;

wire Dn;
wire D1;
wire Dn1;

not(Dn, D);
and(D1, G, D);
and(Dn1, G, Dn);
nor(Qn, D1, Q);
nor(Q, Dn1, Qn);
endmodule // d_latch

module sr_latch_gated(Q, Qn, G, S, R);
output Q;
output Qn;
input G;
input S;
input R;

wire S1;
wire R1;

and(S1, G, S);
and(R1, G, R);
nor(Qn, S1, Q);
nor(Q, R1, Qn);
endmodule // sr_latch_gated
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1 Solution
SyafieqS_Intel
Moderator
226 Views

Hi Jun,


I would suggest you to view you RTL netlist and see the logic if they are designed as intended and the logic and connections have been interpreted correctly by the software. You can use the RTL Viewer and State Machine Viewer to check your design visually before simulation. Tool --> Netlist Viewer --> RTL viewer/state machine viewer.


Analyzing Designs with Quartus II Netlist Viewers

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51013.pdf


Thanks,

Regards


View solution in original post

3 Replies
Jun-Yan-Wu
Beginner
280 Views
Oh sorry~I forgot to attach my waveform photo. Here it is.
SyafieqS_Intel
Moderator
227 Views

Hi Jun,


I would suggest you to view you RTL netlist and see the logic if they are designed as intended and the logic and connections have been interpreted correctly by the software. You can use the RTL Viewer and State Machine Viewer to check your design visually before simulation. Tool --> Netlist Viewer --> RTL viewer/state machine viewer.


Analyzing Designs with Quartus II Netlist Viewers

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51013.pdf


Thanks,

Regards


View solution in original post

SyafieqS_Intel
Moderator
206 Views

We do not receive any response from you to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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