Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

Iteration limit 5000 reached at time X ns.

akhal10
Beginner
‎03-01-2019 01:17 PM
1,280 Views

Hi,

I'm an absolute beginner to this world, i've made a schematic for my design then compiled it (which done successfully) then run the simulation first i hadn't set any input to high and everything worked fine but when i set whatever input to high (except the clock for sure) i got "Iteration limit 5000 reached at time X ns." error, where "X" is the time i set the input pin to high. so what's the problem and how to fix it?

 

environment:

  • Quartus prime lite 18.1 Linux version
0 Kudos

Link Copied

1 Reply
Vicky1
Employee
‎03-04-2019 03:43 AM
832 Views
Hi Abdullah, This issue may occur because of delay.. Could you please provide the schematic & corresponding HDL code for the design used? Regards, Vikas
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.