LCELL removal during logic synthesis

[Altera_Forum]

Per Quartus II help files: 

"An LCELL buffer always consumes one logic cell. It is not removed from a project during logic synthesis."  As found elsewhere in the help files and these forums, this isn't ALWAYS the case. I placed LCELLs to control signal fan-out and force particular delays. The version of Quartus II in use is V9.0. I have established the following settings: Assignments:Settings:Analysis & Synthesis Settings:More Settings...:  Ignore LCELL Buffers Off  Perform WYSIWYG Primitive Resynthesis Off  Remove Redundant Logic Cells Off  Even so, the synthesis is eliminating my LCELLs and leaving warnings like Warning: Synthesized away the following node(s):  Warning: Synthesized away the following LCELL buffer node(s):  Warning (14320): Synthesized away node "Xmit3B_Seq:inst40|OneShot:inst9|inst1"  Warning (14320): Synthesized away node "Xmit3B_Seq:inst40|OneShot:inst5|inst1"  Warning (14320): Synthesized away node "Xmit3B_Seq:inst40|OneShot:inst4|inst1"  I think that these LCELLs are really needed. I chose LCELL because the Help feature stated that they definitely would not be removed during synthesis. How does one put a buffer into the Quartus II bdf file and prevent Quartus compilation from deleting it?

[Altera_Forum]

I'm mainly using VHDL descriptions with synthesis attributes to specify logic delay chains, if necessary in special cases. But as far as I see, LCELLs in a bdf design are generally kept, as specified. The first LCELL in a chain can be possibly "absorbed" by the driving LE. This may be unexpected, but isn't contradicting the specification, I think.

[Altera_Forum]

hmm... if your lcell (or it's input and output)is observed in assignment editor select it and choose the option Netlist Optimizations -> Never Allow. if no lcell input/output are seen, take your input declaration and add keep command for example wire w1 /*synthesis syn_keep*/; to run away from synthesis. if your input is a register do this, reg r1 /*synthesis syn_preserve*/ ; or try /*synthesis syn_noprune*/; . lcells are used to force synthesis to leave you alone with your design, so if lcell gets synthesized i thinks it's more like lcell's input and output variables get synthesized and since lcell is left alone quartus gets rid of it. if in case your lcell output is floating in the air, and input never changes it's value. then quartus will certainly get rid of them no matter how hard you try. also please keep in mind that :  

"Remove Redundant Logic Cells This logic option removes redundant LCELL primitives or WYSIWYG cells. If you turn this option On, the Compiler optimizes a circuit for area and speed. The project-wide option is turned Off by default." from chapter Using Quartus II Verilog HDL & VHDL Integrated Synthesis explains why should we take care about this option. it can be found in settings -> analysis and synthesis settings-> more settings button.