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Altera_Forum

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08-04-2017
07:06 AM

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LFSR doesn't generate random values during simulation Ask

I am new to VHDL. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim.

Here is the link https://stackoverflow.com/questions/45486770/lfsr-doesnt-generate-random-values-during-simulation?no... to the original question as I cannot post the code and problem in here as it exceeds the allowed character length.Link Copied

7 Replies

Altera_Forum

Honored Contributor I

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08-04-2017
07:13 AM

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For a start, most of the bus is just assigned to itself, hence the no changing:

Each set of bits: [15:11] : assigned to itself [10] toggles, as you just xor it with the LSB [9:5] assigned to itself [4] toggles, as just xored with LSB [3:0] assigned to itself. So this will explain what you are seeing. & is the concatenate operator in VHDL, not and.
Altera_Forum

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08-04-2017
07:14 AM

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PS. I dont think you mean ISIM, the picture you show is modelsim. ISIM is XIlinx simulation tool.

Altera_Forum

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08-04-2017
07:21 AM

100 Views

Altera_Forum

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08-04-2017
07:37 AM

100 Views

yes but it is for Fibonacci LFSR not Galois.

Thanks for reply.
Altera_Forum

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08-04-2017
07:38 AM

100 Views

Yes you are right, its ModelSim

Altera_Forum

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08-04-2017
08:13 AM

100 Views

Thanks a lot guys I found why it was not shifting. Here is the working part.

temp_out(15) <= temp_out(0);-- shifting bit temp_out(14) <= temp_out(15); temp_out(13) <= temp_out(14) xor temp_out(0); temp_out(12) <= temp_out(13) xor temp_out(0); temp_out(11) <= temp_out(12); temp_out(10) <= temp_out(11) xor temp_out(0); temp_out(9 downto 0) <= temp_out(10 downto 1);
Altera_Forum

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08-04-2017
08:21 AM

100 Views

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