Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
967 Views

LFSR doesn't generate random values during simulation Ask

I am new to VHDL. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim. 

Here is the link https://stackoverflow.com/questions/45486770/lfsr-doesnt-generate-random-values-during-simulation?no... to the original question as I cannot post the code and problem in here as it exceeds the allowed character length.
0 Kudos
7 Replies
Altera_Forum
Honored Contributor I
100 Views

For a start, most of the bus is just assigned to itself, hence the no changing: 

 

Each set of bits: 

[15:11] : assigned to itself 

[10] toggles, as you just xor it with the LSB 

[9:5] assigned to itself 

[4] toggles, as just xored with LSB 

[3:0] assigned to itself. 

 

So this will explain what you are seeing. 

& is the concatenate operator in VHDL, not and.
Altera_Forum
Honored Contributor I
100 Views

PS. I dont think you mean ISIM, the picture you show is modelsim. ISIM is XIlinx simulation tool.

Altera_Forum
Honored Contributor I
100 Views

 

--- Quote Start ---  

I am new to VHDL. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim. 

Here is the link https://stackoverflow.com/questions/45486770/lfsr-doesnt-generate-random-values-during-simulation?no... to the original question as I cannot post the code and problem in here as it exceeds the allowed character length. 

--- Quote End ---  

 

 

Here is example of 20 bit LFSR(20 downto1): 

 

--clocked process and iitial seed of nonzero 

 

shiftreg(1) <= shiftreg(17) xor shiftreg(20); 

shiftreg(20 downto 2) <= shiftreg(19 downto 1);
Altera_Forum
Honored Contributor I
100 Views

yes but it is for Fibonacci LFSR not Galois. 

Thanks for reply.
Altera_Forum
Honored Contributor I
100 Views

Yes you are right, its ModelSim

Altera_Forum
Honored Contributor I
100 Views

Thanks a lot guys I found why it was not shifting. Here is the working part. 

temp_out(15) <= temp_out(0);-- shifting bit 

temp_out(14) <= temp_out(15); 

temp_out(13) <= temp_out(14) xor temp_out(0); 

temp_out(12) <= temp_out(13) xor temp_out(0); 

temp_out(11) <= temp_out(12); 

temp_out(10) <= temp_out(11) xor temp_out(0); 

temp_out(9 downto 0) <= temp_out(10 downto 1);
Altera_Forum
Honored Contributor I
100 Views

 

--- Quote Start ---  

Yes you are right, its ModelSim 

--- Quote End ---  

 

 

My example is Fibanocci for your case of 16 bits 

 

shiftreg(1) <= shiftreg(16) xor shiftreg(15) xor shiftreg(13) xor shiftreg(4); --feeback taps 

shiftreg(16 downto 2) <= shiftreg(15 downto 1); -- shift
Reply