Intel® Quartus® Prime Software
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LUT Mask

Husam_Iq
Beginner
594 Views

Hello guys,
How can instantiate and initialize the look-up table in the Altera boards family?

the following code is working in Xilinx however it does not work when I run it on Quartus! I don't know what should I change to make it work. I am very new to Quartus software.

I get the following error message: Error (10482): VHDL error at LUT_1.vhd(29): object "LUT6_2" is used but not declared

 

 

 

library ieee;
use ieee.std_logic_1164.all;


entity luts_vhd is
port (
clk : in std_logic;
lut_in : in std_logic_vector(3 downto 0);
lut_out : out std_logic
);
end entity luts_vhd;

architecture rtl of luts_vhd is

signal lut_in_r : std_logic_vector(3 downto 0);
signal lut_out6_d : std_logic;


begin

lut_in_r <= lut_in;
lut_out <= lut_out6_d;


LUT_U0: LUT6_2
generic map (
INIT => X"0000000000000001"
)
port map (
A => lut_in_r(0),
B => lut_in_r(1),
C => lut_in_r(2),
D => lut_in_r(3),
O => lut_out6_d
);

end rtl;

 

 

 

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5 Replies
sstrell
Honored Contributor III
565 Views

You've instantiated LUT6_2 but you have no required component declaration for it, like this:

architecture rtl of luts_vhd is
     component LUT6_2
           generic (INIT: std_logic_vector(15 downto 0);
           port(
                A,B,C,D: in std_logic;
                O: out std_logic);
      end component;
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Husam_Iq
Beginner
526 Views

Thank you for your reply, actually I tried your suggestion but it still not working!

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sstrell
Honored Contributor III
519 Views

Same error message?  Show your full code now.

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Nurina
Employee
557 Views

Hi,

Did the above reply help solve your problem?


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Husam_Iq
Beginner
526 Views
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