LVDS Differential Clock input to single-ended output

[Altera_Forum]

How can I convert an LVDS Clock input to the Cyclone IV GX to a single-ended output? I basically have a 125 MHz differential clock input and want to pass it as a single-ended clock source to another FPGA (MAX10) for synchronization purposes. I believe in Xilinx, I would use the IBUFGDS design element. What's the Altera counterpart? The library that IBUFGDS references to (UNISIM) is proprietary to Xilinx if I'm not mistaken. Is the ALTIOBUF IP Core similar to this? 

 Another question is that how can I connect/reference the negative pin into the design as the top level only declares one port as shown in picture 1 but on pin planner it's connected as two pins as shown in picture 2.   Regards,

[Altera_Forum]

The first question: 

Normally when you have a clock, you mostly have a PLL which generates some other clocks as well. You can easily assign the PLL output clock to an external PLL clock pin (Use your device pin information, there is a dedicated PLL output pin for each PLL). Makes no difference your input clock is single ended or differential. As far as I know, the ALTIOBUF (ALTIOBUF_in, _out, _bidir) is the same if you need to do it using primitives.  The second question: No need to connect/reference the negative pin in the design. In Altera, you can simply connect your positive side pin to the PLL if you have already specified that your port is differential (i.e. you have connected the positive side to the positive pin in a differential port and the negative signal on your board to the negative pin in the same differential port). Quartus infers that it is a differential port and uses appropriate logic.