Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

LVDS RX alignment

Altera_Forum
Honored Contributor II
‎11-29-2010 08:44 PM
1,451 Views

My design implements an LVDS receiver in source synchronous mode in an S3 device. The tx data and clock are from another S3 device.  

 

With a 10:1 serialization, the data at the parallel output of the receiver is mis-aligned, tx bit 0 is received on rx bit 6, tx bit 1 on rx bit 2, etc.. 

 

I am reimplimenting the rx to use the channel data align (cda) feature. My question is, can I use the cda without the DPA or do both have to be used together? 

 

Thanks
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.