Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Logic Analyzer Interface (LAI) using QUARTUS PRIME PRO 20.4

Jamil
Novice
2,180 Views

Screenshot from 2021-06-02 07-03-16.pngHi FPGA community,

 

I am trying to add a very simple logic analyzer interface (LAI) to my design. Once I did this, then I restarted the compilation. But The compilation does not go through. Normally the compilation time for my designs is around 2 h. But now with the LAI after 09 h it still at the beginning of P&R (PLAN).

It was no problem to do the same thing using QUARTUS PRIME PRO 18.1.

 

Does anybody have any Idea, what’s going wrong here?

 

Best Regards

JamilScreenshot from 2021-06-02 07-03-16.png

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6 Replies
sstrell
Honored Contributor III
2,172 Views

How full is your design?  Even though it worked in 18.1, perhaps your design is already pretty full and changed algorithms in 20.4 are preventing a successful P&R.

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Jamil
Novice
2,136 Views

Hi sstrell,

 

Thanks for your reply. No the design is for sure not full. We used approx. 40% of the logic ressources (LABs) and 8% of the memeory ressources.

 

BR

Jamil

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Nurina
Employee
2,150 Views

Hi,


Could it be that your design is using up too much resources? Can you check the Resources Summary in the Analysis & Synthesis report?


Regards,

Nurina


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Jamil
Novice
2,134 Views

Hi Nurina,

 

Yes of course I checked the logic utilizations. About 40% of logic uti (LABs) have been used and about 8% of the memory ressources.

 

I just added a small LAI to the design (6 banks x 4 signals).

 

 

Best Regards

Jamil

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sstrell
Honored Contributor III
2,125 Views

I'd suggest quitting Quartus and then tossing the qdb folder for your project.  It's possible your compilation data is corrupted somehow.  Do a fresh compilation and see if that fixes the issue.

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Nurina
Employee
2,107 Views

Hi,


Did the above reply help?


Regards,

Nurina


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