Logic Analyzer Interface (LAI) using QUARTUS PRIME PRO 20.4

[Jamil]

Hi FPGA community,

I am trying to add a very simple logic analyzer interface (LAI) to my design. Once I did this, then I restarted the compilation. But The compilation does not go through. Normally the compilation time for my designs is around 2 h. But now with the LAI after 09 h it still at the beginning of P&R (PLAN).

It was no problem to do the same thing using QUARTUS PRIME PRO 18.1.

Does anybody have any Idea, what’s going wrong here?

Best Regards

Jamil

[sstrell]

How full is your design?  Even though it worked in 18.1, perhaps your design is already pretty full and changed algorithms in 20.4 are preventing a successful P&R.

[Jamil]

Hi sstrell,

Thanks for your reply. No the design is for sure not full. We used approx. 40% of the logic ressources (LABs) and 8% of the memeory ressources.

BR

Jamil

[Nurina]

Hi,

Could it be that your design is using up too much resources? Can you check the Resources Summary in the Analysis & Synthesis report?

Regards,

Nurina

[Jamil]

Hi Nurina,

Yes of course I checked the logic utilizations. About 40% of logic uti (LABs) have been used and about 8% of the memory ressources.

I just added a small LAI to the design (6 banks x 4 signals).

Best Regards

Jamil

[sstrell]

I'd suggest quitting Quartus and then tossing the qdb folder for your project.  It's possible your compilation data is corrupted somehow.  Do a fresh compilation and see if that fixes the issue.

[Nurina]

Hi,

Did the above reply help?

Regards,

Nurina