Logic Lock Region

[Altera_Forum]

Hi, 

 I am using Stratix-III for my implementation. Is there any way that I force Quartus to only utilize the internal routing resources of a logic lock region for the contents of that LL region? For example I have circuit "A" and I want to explore the minimum LL region size that is required to *place* and *route* circuit "A". Is it possible and if yes how?   Thanks in advance.

[Altera_Forum]

Good question !

[Altera_Forum]

--- Quote Start ---  Hi,  I am using Stratix-III for my implementation. Is there any way that I force Quartus to only utilize the internal routing resources of a logic lock region for the contents of that LL region? For example I have circuit "A" and I want to explore the minimum LL region size that is required to *place* and *route* circuit "A". Is it possible and if yes how?   Thanks in advance.  --- Quote End ---    Hi,  as far a s I know you could only prevent the placement of non-logiclock member inside the LL region. You can set that in the LogicLock Region Properties setting in the general tab under "Reserved".