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Valued Contributor III
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altera_reserved_tck timing violation

Hi all, 

 

I am running niosII UDPoffload reference design from (http://www.alterawiki.com/wiki/nios_ii_udp_offload_example). Everything goes on well until I met with removal timing violation on altera_reserved_tck of -2.243ns.  

 

The tck constraints look like following:# ---------------------------------------------------------------------------# JTAG interface input and output delays# --------------------------------------------------------------------------- 

 

set_input_delay \  

-clock [ get_clocks altera_reserved_tck ] \  

10.0 \  

[ get_ports { \  

altera_reserved_tms \  

altera_reserved_tdi \  

} ]  

 

set_output_delay \  

-clock [ get_clocks altera_reserved_tck ] \  

10.0 \  

[ get_ports { altera_reserved_tdo } ]  

 

I noticed the following two lines are commented out:# create_clock -period 10MHz {altera_reserved_tck}# set_clock_groups -asynchronous -group {altera_reserved_tck} 

 

What's the root cause of these removal timing violations? Should I uncomment the above two lines (I assume altera tools will automatically create this altera_reserved_tck instead of user manually create in user's sdc, am I right)?  

 

FYI, the timing report is following: 

Critical Warning: Timing requirements not met 

Info: Worst-case removal slack is -2.243 

Info: Slack End Point TNS Clock 

Info: ========= ============= ===================== 

Info: -2.243 -2.243 altera_reserved_tck 

Info: 0.973 0.000 test_sys_sopc_inst|the_ddr_ram|ddr_ram_controller_phy_inst|ddr_ram_phy_inst|ddr_ram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[2] 

Info: 1.004 0.000 test_sys_sopc_inst|the_ddr_ram|ddr_ram_controller_phy_inst|ddr_ram_phy_inst|ddr_ram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[0] 

Info: 1.007 0.000 test_sys_sopc_inst|the_ddr_ram|ddr_ram_controller_phy_inst|ddr_ram_phy_inst|ddr_ram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] 

Info: 1.017 0.000 clkin_125 

Info: 1.024 0.000 test_sys_sopc_inst|the_ddr_ram|ddr_ram_controller_phy_inst|ddr_ram_phy_inst|ddr_ram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock 

Info: 1.393 0.000 test_sys_sopc_inst|the_ddr_ram|ddr_ram_controller_phy_inst|ddr_ram_phy_inst|ddr_ram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[4] 

Info: 2.094 0.000 test_sys_sopc_inst|the_enet_pll|the_pll|altpll_component|auto_generated|pll1|clk[1] 

Info: 2.521 0.000 test_sys_sopc_inst|the_ddr_ram|ddr_ram_controller_phy_inst|ddr_ram_phy_inst|ddr_ram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] 

Info: The Metastability Analysis global option is set to OFF. 

Warning: The launch and latch times for the relationship between source clock: altera_reserved_tck and destination clock: test_sys_sopc_inst|the_enet_pll|the_pll|altpll_component|auto_generated|pll1|clk[1] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. 

Warning: The launch and latch times for the relationship between source clock: altera_reserved_tck and destination clock: test_sys_sopc_inst|the_enet_pll|the_pll|altpll_component|auto_generated|pll1|clk[1] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
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Highlighted
Valued Contributor III
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Re: altera_reserved_tck timing violation

Yes, you should uncomment those two lines in order to avoid the fake timing violation warning. 

I had the same problem. If you search the forum, you'll find a few posts which refer to this anomaly. 

Regards
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