LogicLock Arria10 issues with Platform Designer projects

[EGrub]

I'm having a big Platform Designer project with Quartus Prime 18.1 (there is a good reason why I use this version but should not be the topic of this issue)

With an Arria10 the Platform Designer generates the hierarchy names with version number and random IDs (see snipped in the hierarchy.png).
If I would like to have a logic lock now on the "ADC" module to locate it near the I/Os I would need to use wildcards because the random number (red marked in the image) changes with every Platform Designer generation.

But if I use wildcards on the hierarchy the Logic Lock does not work and throws the warning:

Warning (140116): One or more LogicLock region membership assignments are unused

and

Warning (140117): "*:calibration|*:adc" in region "calib"

So now the question: how to overcome that?

[sstrell]

You shouldn't need to use Logic Lock regions if you have timing constraints set up correctly.  Where are you seeing an issue (timing report?) that prompted you to add LL regions like this?

And is that an off-the-shelf IP or your own custom IP?  I don't recall a hard (or soft) ADC off-the-shelf in A10.

[EGrub]

My experience is that if one directs the fitter with some logic locks for some parts of the design, especially those where timing violations occur randomly, the fitting result is much better and fitting is done faster!
No it is my own IP for an high speed external ADC.
I used this in a Cyclone V and Arria V and made good experience with LL there.
Nevertheless even if it wouldn't be necessary this random naming of Platform Designer seems to "kill" the LL feature which is really bad in my opinion.

[EGrub]

I need to push it up again, until now there was no suggestion to solve the problem.
As this topic is now open for more than a month I request a proper reply from an Intel FPGA employee!

BR Erich

[RichardTanSY_Altera]

Hi @EGrub 

Sorry for the late response. The engineering team is working on this. 
May I know are you using Quartus Standard or Quartus Pro 18.1 version?

Best Regards,

Richard Tan

[EGrub]

Hi Richard!

I'm using the Standard version!
Do you have any information when there will be a solution?

It seems that the Signal Tap Logic Analyzer has the same issue!

I am working with Quartus 18.1 Standard because this is the last version which does not need Windows Subsystems for the NIOS generation.

I really need a solution for that issue!

BR

Erich

[RichardTanSY_Altera]

Hi @EGrub  

Here's the feedback I get from the engineering team:

Here are some things to try:

1. "*|*:calibration|*:adc" 
We should try adding another (or more) leading wildcard: *| , as wildcards sometimes do not cross hierarchical boundaries.

2. Is adc is a hierarchy or bus? Try "*|*:calibration|*:adc|*" or "*|*:calibration|*:adc[*]"

3. Set logiclock region with absolute name, and fix the name whenever you re-ran platform designer.

Let me know whether it helps. 

Best Regards,

Richard Tan

[RichardTanSY_Altera]

Hi @EGrub 

Based on the latest feedback, do you able to get it works? 

Best Regards,

Richard Tan

[EGrub]

Hi Richard!

Solution 2 seems to work: "*|*:calibration|*:adc|*"

And I tried something similar than "*|*:calibration|*:dac|output[*]" and that worked as well!

May it be that if one of the logic locks fails due to an error the others are failing as well?

I changed the first few logic locks for testing reason and the warnings of the other logic locks vanished as well?!

BR

Erich

[RichardTanSY_Altera]

Hi @EGrub 

I am glad that the solution works for you. Unfortunately, the thread has been transition to the community support due to long idle time since my last reply. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.