Looking for advice on using OpenCL FPGA for data acquisition

Altera_Forum · ‎02-05-2016

Greetings!

We are trying to implement an image acquisition hardware based on OpenCL FPGA and I'm wondering if anyone could provide some advice.

Specifically, we would like to write host and kernel code with Altera OpenCL SDK, and implement the following properties on the FPGA:

1) generic digital or analog ios to communicate with shutter, sensors, cameras (onboard IOs or the HSMC card with a daughter board);

2) asynchronous fifo channels for buffering incoming data and transferring data to host;

3) interruptions or control signals that allow the host and the kernel to communicate with each other about their status (data transfer completed, acquisition finished, FIFO full, etc.).

I read the Altera OpenCL manual but couldn't find details to address my concerns above. Googling the topic didn't help much either.

Will anyone recommend a development kit that meets our needs? Or, any comments & suggestions are greatly appreciated!

Thanks,

Bing

Altera_Forum · ‎02-09-2016

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1) generic digital or analog IOs to communicate with shutter, sensors, cameras (onboard IOs or the HSMC card with a daughter board);

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These sort of low level tasks may not be well suited for OpenCL, but it I'm not quite sure.

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2) asynchronous FIFO channels for buffering incoming data and transferring data to host;

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This will be extremely easy and convenient with OpenCL. The SDK will basically do all the work for you.

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3) interruptions or control signals that allow the host and the kernel to communicate with each other about their status (data transfer completed, acquisition finished, FIFO full, etc.).

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Communication between kernels is usually realized with the Altera channel extension for OpenCL. Communication with the host generally uses memory accesses. If you only have to synchronize host code with OpenCL kernel completion, there are function calls to do just that.

If you come from a VHDL/VERILOG background, let me just tell you that OpenCL for FPGAs is very very high level programming in comparison.

Altera_Forum · ‎02-09-2016

Hi Mscharrer,

Thanks very much for your reply!

It's great that the FIFO issue can be dealt with by the SDK.

Regarding interruptions or control signals, what I'd like to have is a way for the host and the kernel to interactively communicate with each other during the execution of the kernel. For example, when the host is notified that FIFO has the data ready, it will start pulling data from FIFO. Meanwhile, if the kernel is notified that the host has finished reading data, it will resume buffering new data. Did you mean that such notifications are realized by some kind of global memory that can be accessed by both the host and the kernel?

I have some experience with high level programming languages like C++ and Java, but new to FPGA and have no experience with VHDL/VERILOG. That's why I was wondering whether OpenCL would give me an easier jump start than learning low-level HDLs.

Thanks,

Bing