Max 10 ADC does not show as included in Project Summary Compilation

[AKohl3]

Hi,

Attached is the project for which I have followed all the right steps to include an ADC in my project but on the viewing the project summary on compilation, the ADC still shows 0/1 in project.

[JonWay_C_Intel]

Hi @AKohl3​ 

Could you download one of the MAX 10 ADC examples from the design store, and compare it against your project.

You can try this simple design first

https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/max-10-adc-with-threshold-violation-detection/

[AKohl3]

Looks like I have to link the Avalon_Bridge module to invoke my ADC module even if I'm not trying to use JTAG to monitor or observe the performance of the ADC. I was only looking to implement a simple ADC module with core control sending a soft command for the channel to digitize. So, the Avalon bridge is a must for ADC use?

[JonWay_C_Intel]

Hi @AKohl3​ 

By Avalon Bridge, do you mean the the JTAG-Avalon Master Bridge?

If yes, you will only need this if you are sending commands from system console (via JTAG).

May I know, when you say “sending soft commands”, how are you sending commands to the ADC? JTAG? NIOS? State machine?