Maximum SPI clock (SCLK) rate of SPI Intel FPGA IP

[Fuad1]

In an Arria 10 SoC design, what is the maximum supported SPI clock rate/data rate of the Intel FPGA SPI IP for slave and master modes?

Regards,

[KennyTan_Altera]

We used bit rate for the calculation, you can check the information here https://www.intel.com/content/www/us/en/docs/programmable/683711/22-3/features-of-the-spi-controller.html

[Fuad1]

Dear Kenny,

What you provided is the data rates for the HPS SPI controller. Would you please provide the maximum supported SPI clock rate/data rate of the Intel FPGA SPI IP (Altera Avalon 4 wire serial) for slave and master modes? Thank you.

Regards,

[FvM]

Hi,
maximal master sclk rate is clk/2 (clock divider 2, 4, 8 ...). Maximal slave sclk rate is clk/3 if read the doc correctly.

[KennyTan_Altera]

That is correct, do let us know if you have further queries?

[Fuad1]

Thank you for answering my question.

Regards,

[KennyTan_Altera]

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