Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17237 Discussions

Maximum frequency with QuartusII

Altera_Forum
Honored Contributor II
‎11-29-2012 10:18 AM
1,057 Views

Hi everyone, 

 

I have a simple question from an expert of the EDA tools. If I set a fmax of say 300 MHz and the QuartusII STA reports the fmax achieved is 280MHz. The STA also provides a list of failing paths. If suppose I change the fmax to 275MHz and run only the STA without recompiling the whole design for the new fmax. The STA will provide no failing paths for this fmax. Will this image work in FPGA at the new fmax. I haven't yet tried this into the FPGA for non availability of the test board. I think it should work.  

 

Thanks,
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎11-29-2012 12:30 PM
333 Views

Yes, it will. I would recommend running Processing -> Start -> TimeQuest, which will run the full TQ flow, i.e. it will analyze all timing models which is a normal part of sign-off flow, but if it passes you're good to go. (Another example I see is a design failing timing, and the user realizes the failing paths can be false path'd or multicycled. They change the .sdc, re-run TQ, and if it passes they're good...)

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.