I am trying to determine the GFLOPs per Watt for the aocl kernels that I wrote. I am just wondering if there is any way to measure or estimate runtime power usage of FPGA/board in software? I use de5-net development board. Thanks! Regards, Ryan
I pass the project through Quartus II, make place-route-implement, and then run the power estimation tool. Not very accurate without simulation data, but you can get an idea.
Thank you George! I'll try that. I know it's possible to use pci-e riser card and current probe but was just trying to see if there are simpler methods.
