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Altera_Forum
Honored Contributor I
866 Views

Meeting timing requirements with async signal.

Hey everyone. 

I've been studying computer architecture for some time, but I'm still new to circuit design and VHDL, so this might be obvious, but I still need help. 

I'm developing a MIPS style processor in VHDL, and so far had no problem with timing, but while implementing the store instruction, I can't seem to meet the timing requirements, and it only happens when I enable writing to RAM. 

 

The way I've been working is to use a negated clock on a controller block, that sets up the needed signals and enables other components that will be used on the next clock edge. For the store instruction, I can implement everything with no problems, but as soon as I write the line to enable the "write enable" signal, the timing constraints are not met and the max frequency drastically reduces. It doesn't make any sense to me since all I'm doing is enabling one bit. The controller, on the falling edge, enables the RAM's Write Enable signal. The RAM, on the next rising edge, receives a clock pulse and writes data. It works fine on the load instructions, but not in the store one. 

 

As I said, being new to circuit design and VHDL, I have only basic knowledge of timing, and I can't seem to find somewhere to learn about it, besides 1000 page books, and I really don't have the time to put into that, so I'd appreciate anything I could read for a better understanding of the subject. 

 

The code for my project is not small, but I think all that matters for the question is the controller, so here is the line I was talking about: 

https://github.com/viniciuslambardozzi/quanta/blob/master/hardware/quanta/src/vhdl/component/control... 

I feel like a complete amateur working on this, even though it's a college project, so don't judge the bad code, I'm trying my best. 

 

I'd appreciate any help, so thanks in advance.
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Altera_Forum
Honored Contributor I
27 Views

Not many pointers to your problem. The code does look like large mux but should not by itself be the problem in modern FPGAs. 

Your problem seems outside and my suspicion is on clock and its inversion? and you also title your post with async? you need to describe why and how you invert clock and what is this async to do with timing.
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