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I'm trying to tailor a larger memory to my needs. This is for a Cyclone II, which has only M4K memory blocks. It shall be a simple dual port, one port writes, another reads, with different clocks.
Precision helps my application, so I'm trying to exploit that the blocks can be 9 bits wide (or multiples of it), instead of 8. Now I'm puzzled that configuring for 9 bit width costs me extra blocks!? (Or is this a bug in the resource estimation?) Example: Configure a memory 8 bits wide, 512 words deep. Resource usage is one M4K. Increase width to 9 bit: still 1 M4K, as expected. Double the depth to 1024 words, gives 3 M4Ks?! Reduce width to 8 bit: back to the normal 2 M4Ks. Similar strangeness for wider and deeper. My real case is 128 vs. 144 bits wide, 2048 words deep. Needs 72 M4Ks instead of 64 for increasing the width to what shall be available already. Where is this coming from? Are there better ways to design memory? Also, I'd like to have a non power of two size (within M4K granularity, of course). Thanks Jörg Edit: Tested with Quartus 11 and 12, Windows and Linux.Link Copied
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What is most likely happening is the tool is optimizing for memory block depth first vs width. So in your 2k deep solution, it's using the M4K in the 2kx2 configuration. and stitching them together to get your width. This probably gives you the best timing optimization vs area. (or ram utilization)
If the build is completing, I wouldn't worry about it. If your build is failing, try to optimize for area in the Quartus settings and see if that helps. If that fails, try to build your desired memory from smaller 512 x 9 blocks and stitch them together yourself. This really should be a fitting pass optimization, where it should try it both ways depending on the limiting factor (speed, vs ram block utilization). If it's failing with a can't fit, I would open a service request with Altera to request this feature. Regards Pete- Mark as New
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I see, didn't think of the 2K*2 configuration. Way easier to bundle such slices to a wider memory, because no address decoding is necessary.
In that case, the configuration is somewhat misleading, it offers me steps of 8 and 9 bits where it could even be steps of 2. Jörg- Mark as New
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In the wizard, I just found the selector "Set the maximum block depth to"..."words".
It does the desired, I can limit it to 512 words and it will compose the memory with 9 bit wide blocks, at the expense of more logic. Case solved, sorry, I could have found that RTFM. Jörg
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