Merge simplex transceiver (tx and rx lanes) PHYs in Quartus® Prime Platform Designer on Agilex F014

[Winston_Sun]

Hi,

I'm trying to allocate a 8 lanes tx and a 4 lanes rx in the E-tile bank 9A connecting to the same QSFPDD1 (8 pins for tx_serial[] output ports and 4 pins for rx_serial[] output ports) as shown in the figure 1. Since by default, when using IP JESD204C simplex transmitter and receiver IPs, the coupled-pair rx or tx channel are tied off, I want to merge multiple jesd204C IP blocks to maximize transceiver channel utilization.  I used wire-level connections in platform designer to allow the transceiver TX and RX PHYs to share the same address space, figure 2    ( https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/hsio/2020/how-do-i-merge-simplex-transceiver-phys-inside-the-intel--quartu.html  ) and also I added XCVR_RECONFIG_GROUP in the QSF assignments as follows:

set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to rx_serial_data[0] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to rx_serial_data[1] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to rx_serial_data[2]
set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to rx_serial_data[3] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to rx_serial_data_n[0]  
set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to rx_serial_data_n[1]
set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to rx_serial_data_n[2] set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to rx_serial_data_n[3]

set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to tx_serial_data[0] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to tx_serial_data[1] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to tx_serial_data[2] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to tx_serial_data[3] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 4 -to tx_serial_data[4] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 5 -to tx_serial_data[5] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 6 -to tx_serial_data[6] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 7 -to tx_serial_data[7] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to tx_serial_data_n[0] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to tx_serial_data_n[1] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to tx_serial_data_n[2] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to tx_serial_data_n[3] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 4 -to tx_serial_data_n[4] 
set_instance_assignment -name XCVR_RECONFIG_GROUP 5 -to tx_serial_data_n[5]
set_instance_assignment -name XCVR_RECONFIG_GROUP 6 -to tx_serial_data_n[6]
set_instance_assignment -name XCVR_RECONFIG_GROUP 7 -to tx_serial_data_n[7]

 (chapter 6.14 in 

(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf)

After doing the aboves steps, I received this error (four similar errors about merging conflicts):

The Fitter cannot place 4 periphery component(s) due to conflicts with existing constraints (4 HSSI_C3_DUPLEX_CHANNEL_CLUSTER(s)).

The Fitter cannot place logic HSSI_C3_DUPLEX_CHANNEL_CLUSTER that is part of JESD204C Intel FPGA IP j204c_tx_ip_intel_jesd204c_intel_jesd204c_110_cs5x7ii in region (332, 0) to (334, 111), to which it is constrained, because there are no valid locations in the region for logic of this type.

No legal location could be found out of 1 considered location(s). Location(s) already occupied and components cannot be merged.

The error seems to be when merging the 8 TX pins with the 4 RX pins, it failed, causing the 4 merging conflicts.

One thing I notice that looks weird is the Address map (figure 3).  The address for j204c_tx_ip.intel_jesd204c_j204c_reconfig and j204c_rx_ip.intel_jesd204c_j204c_reconfig, ranges are 0x0000_0000 - 0x0000_0000 and 0x0000_0001 - 0x0000_0001 respectively.  

Is there anything I miss when merging 2 simplex PHYs? Any help would be appreciated.

[CheePin_C_Intel]

Hi,

As I understand it, you have some inquiries merging of simplex instances. Based on my understanding, the two instance will need to be of the same number of channel. To facilitate the debugging, I would recommend you to start with two 4 channels simplex instances in RTL and try on the merging. Once it is successful, you may move to Platform Designer to try out merging. This would be helpful to narrow down issues if there is any arise. 

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[Winston_Sun]

Hi Chee,

I tried merging simplex transmitter and receiver PHY (4T4R) and it still gives the same error about pin conflicts. In page 37 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf , it says "For simplex variants with E-tile transceiver, the underneath transceiver is in duplex mode. The merging of independent TX and RX within a transceiver channel is not supported in this version",

Does Agilex E-tile supports merging simplex jesd204c transmitter and receiver PHY in the first place? If yes, is there any example designs or documents I can refer to?

Thanks,

Winston

[CheePin_C_Intel]

Hi Winston,

Thanks for your update and clarification that you are using E-Tile transceivers. For your information, due to the underneath architecture, when E-Tile is put to simplex mode, the unused pair (TX or RX) will be powered down. This restriction is tile dependent. Therefore, in the Agilex E-tile, similar restriction should apply. Sorry for the inconvenience. As a workaround, you might want to explore H-Tile if you merging is required.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin 

[Winston_Sun]

Hi Chee,

Thanks for your clarification! One more question, when I read the JESD204C intel IP document, it says that Device Support on the JESD204C is Agilex (e-tile) or Stratix 10 (e-tile), shown in the attached screenshot. Does this mean that I cannot use H-tiles for JESD204C? So I can only pick either to merge simplex PHY (H-tiles) or using JESD204C IP block (E-tiles)?

Thanks again,

Winston

[CheePin_C_Intel]

Hi Winston,

Sorry for the delay. I might have overlooked the notification from your previous post. Sorry for the inconvenience.

Regarding your inquiries on the device support, yes, your understanding is correct. JESD204C is currently supported in E-Tile only.