Metastability test inside FPGA

[Altera_Forum]

Hi all! 

 I'm working with DE-0 NANO and trying to create a simple design to show the importance of making timing constraints. I think it will be very representative if a part of design that doesn't meet timing, falls into a metastable state and after that a problem will be fixed adding constraints.  Can someone help me with any ideas, how to create a code which will mostly representative crashes if a metastable situation occurs (internal counter stops, dead state enters, etc)?  And how to visualize it better (signal tap, signal probe, iLEDs maybe).    Thanks in advance.

[Altera_Forum]

--- Quote Start ---  Hi all!  I'm working with DE-0 NANO and trying to create a simple design to show the importance of making timing constraints. I think it will be very representative if a part of design that doesn't meet timing, falls into a metastable state and after that a problem will be fixed adding constraints.  Can someone help me with any ideas, how to create a code which will mostly representative crashes if a metastable situation occurs (internal counter stops, dead state enters, etc)?  And how to visualize it better (signal tap, signal probe, iLEDs maybe).    Thanks in advance.  --- Quote End ---    There is one here: http://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0ccqqfjaa&url=http%3a%2f%2fwww.altera.co.uk%2fliterature%2fwp%2fwp-01082-quartus-ii-metastability.pdf&ei=yvi0vie9d_om7abliyg4bw&usg=afqjcng_grhb27s1lwq24tre8frbxhbila&sig2=gzpxe4z9iaqyeud6gle80q

[Altera_Forum]

Hi, kaz, thank you for your answer! 

 Did you mean Figure 4. - Test Circuit Structure for Metastability Characterization?  In that figure there are two destination registers, one rising_edge triggered and one falling edge triggered. And if the data after synchronizer is not the same on rising edge and the falling edge of the clkb, we will receive an error. That can be, for example, if the synchronizer enters metastable state and resolves only after the falling edge of clkb, so then the next falling edge of a clkb occurs we will see an error.  But it is not representative as I think, it will be better if I can stop state machine or maybe reverse the counter. I mean, than some register enters metastable state, and we didn't isolate it from our code with a synhcronizer, we can make a code which will not work as we expect.   Our HDL code can only operate with '0' and '1', we can see that after metastable register resolves, our data can be not '0' but '1', or vice versa, and there will be a bug. That's will be a wrong detection. But I think (maybe I'm wrong), that there is a different type of bug generated by metastability. I mean, if our register that drives states of state machine, for example, receives a metastable value, it can direct us to the state, from which we cannot escape, for example. I mean what can happen, if our code makes a decision not after the metastable register resolves, but in time then it exactly outputs metastable value.

[Altera_Forum]

Yes it is figure 4 

 The metastable state should resolve (be sampled) as either 0 or 1 (there is no other third state, logically).

[Altera_Forum]

Thank you, kaz. Am i right, that you mean that it is impossible to sample metastable condition in design, only '1' or '0'?

[Altera_Forum]

--- Quote Start ---  Thank you, kaz. Am i right, that you mean that it is impossible to sample metastable condition in design, only '1' or '0'?  --- Quote End ---    correct. just same as floating input. If an fpga input is not connected it will be floating and may start as 1 or 0 or alternate by touching it

[Altera_Forum]

Thank you very much, kaz.

[Altera_Forum]

kaz, sorry, I have one more question. Is it true that, for example, to test input port of FPGA on metastability, I can use scheme (Figure 4. - Test Circuit Structure for Metastability Characterization)?

[Altera_Forum]

--- Quote Start ---  kaz, sorry, I have one more question. Is it true that, for example, to test input port of FPGA on metastability, I can use scheme (Figure 4. - Test Circuit Structure for Metastability Characterization)?  --- Quote End ---    No, that scheme is used to measure MTBF of fpga registers. It has its own two unrelated clock inputs. It is not about specific path measurement. For a specific reg to reg path detection of metastability: first if your timing passes including correct io constraints then you can depend on tool's report and need not do any metastability detection. If you are doing research then you can try a scheme based on xor say of two registers driven by one input (duplicates) and xor them to see if they sample differently. Just a thought!

[Altera_Forum]

kaz, thank you for your answer. As about timing in TimeQuest that is clear. 

 As I understand, your suggested scheme with two registers driven by one input should work like that: One register could go metastable and resolve '1' and second can resolve '0' and that is the error signal. Thank you!