Good dayI have attempted to migrate a design from Quartus v15.0 to Quartus v16.1.2. I updated all IP components used and worked through the port_diff_report, no major changes. When compiling the project, the design no longer fits. From comparing the map.rpt reports, in the Analysis & synthesis Summary I can see both cases result in the same number of total logic elements. When I compare the fit.rpt reports, I can see the following: - The v16.1 fit resulted in fewer "Combinational with a register" elements, hence Total logic elements no overflow. - From the fitter output v16.1 required 146 LABs, where v15 only required 144. - v16.1 requires 14M9Ks, whereas v15 only used 12. - Connected to this point I noticed that v15 assigned 2 Clock control blocks, v16.1 did not assign these. My main question at this stage is whether I am missing some fitting settings (I have played with the settings, but could not get the design to fit as yet), or whether these differences are as a result of the migration from v15 to v16. From the fitter report the fitter settings were the same in v16 as in v15.) As additional information, I tried to build the v15 project in v16 without updating the IPConfig (simply building v15 project as is) and I got the same result (design did not fit) Any advice or comments as to why the size varies so much between v15 and v16 would be greatly appreciated. Kind regards Gerhard
In the fitter report you'll find an entry called "Resource Utilization by Entity". It will give you resource usage for each entity. You can compare the reports for both versions to check which entity uses now more resources. Then look for that entity name in the compiler warnings and see if you can find any message explaining why it is using more resources.