Minuimum Pulse Width timing violation with Cyclone IV internal oscillator

Altera_Forum · ‎09-24-2014

I have a Cyclone IV design which uses the altint_osc megafunction. When I run Timequest I get a minimum pulse width violation on one node which appears to be internal to altint_osc.

My SDC file is:

#  Clock constraints#  External 24 MHz clock
create_clock -name "MainClk" -period 41.667ns  #  Internal RC oscillator, 80 MHz max
create_clock -name "IntClk" -period 12.5ns {intosc_altint_osc_i57:intosc|wire_cycloneiii_oscillator1_clkout}
#  Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
#  Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
#  MainClk & IntClk are asynchronous
set_clock_groups -asynchronous -group {MainClk} -group {IntClk}

My understanding is that the internal oscillator has a nominal frequency of 60 MHz and a tolerance of +/- 20 MHz, hence the 12.5ns period in the SDC.

The relevant part of the timing analysis report is

Slack Actual Width Required Width Type Clock Clock Edge Target

-8.730 12.500 21.230 Min Period IntClk Rise intosc_altint_osc_i57:intosc|cycloneiii_oscillator1~OBSERVABLEOSCENAREG

-4.526 6.250 10.776 High Pulse Width IntClk Rise intosc_altint_osc_i57:intosc|cycloneiii_oscillator1~OBSERVABLEOSCENAREG

-4.415 6.250 10.665 Low Pulse Width IntClk Rise intosc_altint_osc_i57:intosc|cycloneiii_oscillator1~OBSERVABLEOSCENAREG

The 'oscena' input on the alt_intosc is tied high in my code.

As a sanity check, I created a test output driven from the internal oscillator which blinks an LED at 1 Hz, assuming the nominal 60 MHz frequency. This works and gives roughly the correct frequency.

The top line of the report suggests the maximum frequency is about 47 MHz.

The IntClk line in the SDC was based on reading this thread, I did a node search for altintosc in Assignment Editor and pasted the result in:

http://www.alteraforum.com/forum/archive/index.php/t-42374.html

What am I doing wrong?

Altera_Forum · ‎04-15-2015

A quick follow up, I seem to have solved my own problem, though quite by accident...

I wanted to make the internal clock easier to find when using SignalTap etc. The output of the alt_int_osc megafunction was mapped to a signal int_clk in the top level of my code, so I added a synthesis directive

    attribute keep : boolean;
    attribute keep of int_clk : signal is true;

then changed the entry in my .sdc to reference this node

# Internal RC oscillator, 80 MHz max
create_clock -name "IntClk" -period 12.5ns {int_clk}

The design now passes timing analysis, the minimum pulse width has 5.6 ns of slack. I can only assume that as the clock signal is now buffered by an LCELL, the minimum pulse width constraint isn't being applied to the internal node of the megafunction which had the minimum pulse width problem.

I'm posting this in case anyone else runs into the same problem, but from what I can gather, using the internal oscillator in the application code seems to be a very rare occurrence.

Altera_Forum · ‎08-16-2016

Thanks Rhydian, this was very helpful information for me!

Ralf