Mismatched Nodes

[Altera_Forum]

I am designing a 4 bit ripple adder using input and output buses. They are named A[3..0],B[3..0] and Sum[3..0]. When I try to simulate the circuit though I get these errors: 

Warning: Wrong node type and/or width for node "|AdderRipple|A" in vector source file. Node in design is of type Bus and of width 4, but node in vector source file is of type 9-Level and of width 1.  Error: Can't simulate mismatched node types Warning: Wrong node type and/or width for node "|AdderRipple|B" in vector source file. Node in design is of type Bus and of width 4, but node in vector source file is of type 9-Level and of width 1.  Error: Can't simulate mismatched node types Warning: Wrong node type and/or width for node "|AdderRipple|Sum" in vector source file. Node in design is of type Bus and of width 4, but node in vector source file is of type 9-Level and of width 1.  Error: Can't simulate mismatched node types Error: Quartus II Simulator was unsuccessful. 3 errors, 3 warnings  What am I doing wrong here?

[Altera_Forum]

--- Quote Start ---  I am designing a 4 bit ripple adder using input and output buses. They are named A[3..0],B[3..0] and Sum[3..0]. When I try to simulate the circuit though I get these errors: Warning: Wrong node type and/or width for node "|AdderRipple|A" in vector source file. Node in design is of type Bus and of width 4, but node in vector source file is of type 9-Level and of width 1.  Error: Can't simulate mismatched node types Warning: Wrong node type and/or width for node "|AdderRipple|B" in vector source file. Node in design is of type Bus and of width 4, but node in vector source file is of type 9-Level and of width 1.  Error: Can't simulate mismatched node types Warning: Wrong node type and/or width for node "|AdderRipple|Sum" in vector source file. Node in design is of type Bus and of width 4, but node in vector source file is of type 9-Level and of width 1.  Error: Can't simulate mismatched node types Error: Quartus II Simulator was unsuccessful. 3 errors, 3 warnings  What am I doing wrong here?  --- Quote End ---    Hi,  how did you define your inputs in the vector file ? I assume you have a small test project. Can you post it in the forum ?  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  how did you define your inputs in the vector file ? I assume you have a small test project. Can you post it in the forum ?  Kind regards  GPK  --- Quote End ---   Sure, here is my project: http://www.mediafire.com/download.php?ywjlwnedmvu  AdderXOR is the full adder, and AdderRipple is the four bit ripple adder.

[Altera_Forum]

--- Quote Start ---  Sure, here is my project: http://www.mediafire.com/download.php?ywjlwnedmvu  AdderXOR is the full adder, and AdderRipple is the four bit ripple adder.  --- Quote End ---     Hi,  I could not get access to your project. Can you please generate a zip-File of your project and post it directly in the forum ?  Kind regards  GPK

[Altera_Forum]

I didn't know that this forum let you add attachments. So I've attached the zip file to this post. 

 Thanks :)

[Altera_Forum]

--- Quote Start ---  I didn't know that this forum let you add attachments. So I've attached the zip file to this post.  Thanks :)  --- Quote End ---    Hi,  I look into your project and found that you have specified your input signal A and B with the width of 1. You can change the setting by opening your .vwf, select e.g input A, right mouse click , properties and change bus width to 4. This should solve your probem.  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  I look into your project and found that you have specified your input signal A and B with the width of 1. You can change the setting by opening your .vwf, select e.g input A, right mouse click , properties and change bus width to 4. This should solve your probem.  Kind regards  GPK  --- Quote End ---    Hi, What a kind man you are! My project have the same question,Can you help me? Thank you  below is my vhdl source file: library ieee; use ieee.std_logic_1164.all;  entity yinliaoji is  port(  A: in std_logic;  B: in std_logic;  Y: out std_logic;  Z: out std_logic;  Q: buffer std_logic_vector(1 downto 0)  ); end yinliaoji;  architecture behave of yinliaoji is  begin  process(A,B,Q)  begin    if Q="00" and A='0' and B='0'then Q<="00";Y<='0';Z<='0';  elsif Q="00" and A='0' and B='1'then Q<="01";Y<='0';Z<='0';  elsif Q="00" and A='1' and B='0'then Q<="10";Y<='0';Z<='0';  elsif Q="01" and A='0' and B='0'then Q<="01";Y<='0';Z<='0';  elsif Q="01" and A='0' and B='1' then Q<="10";Y<='0';Z<='0';  elsif Q="01" and A='1' and B='0' then Q<="00";Y<='1';Z<='0';  elsif Q="10" and A='0' and B='0' then Q<="10";Y<='0';Z<='0';  elsif Q="10" and A='0' and B='1' then Q<="00";Y<='1';Z<='0';  elsif Q="00" and A='1' and B='0' then Q<="00";Y<='1';Z<='1';  end if;    end process; end behave;

[Altera_Forum]

--- Quote Start ---  Hi, What a kind man you are! My project have the same question,Can you help me? Thank you  below is my vhdl source file: library ieee; use ieee.std_logic_1164.all;  entity yinliaoji is  port(  A: in std_logic;  B: in std_logic;  Y: out std_logic;  Z: out std_logic;  Q: buffer std_logic_vector(1 downto 0)  ); end yinliaoji;  architecture behave of yinliaoji is  begin  process(A,B,Q)  begin    if Q="00" and A='0' and B='0'then Q<="00";Y<='0';Z<='0';  elsif Q="00" and A='0' and B='1'then Q<="01";Y<='0';Z<='0';  elsif Q="00" and A='1' and B='0'then Q<="10";Y<='0';Z<='0';  elsif Q="01" and A='0' and B='0'then Q<="01";Y<='0';Z<='0';  elsif Q="01" and A='0' and B='1' then Q<="10";Y<='0';Z<='0';  elsif Q="01" and A='1' and B='0' then Q<="00";Y<='1';Z<='0';  elsif Q="10" and A='0' and B='0' then Q<="10";Y<='0';Z<='0';  elsif Q="10" and A='0' and B='1' then Q<="00";Y<='1';Z<='0';  elsif Q="00" and A='1' and B='0' then Q<="00";Y<='1';Z<='1';  end if;    end process; end behave;  --- Quote End ---    Hi,  only o be sure, you have also a problem with a vwf-file for simulation ?  Kind regards  GPK

[Altera_Forum]

Hi 

I'am sorry can't reply you in time because I had classes this afertnoon.After checked the question my teacher ordered,I have solve the problem by redesign the program.Thank you.  Good night.

[Altera_Forum]

After you click simulate button, you will face above errors, then open the Simulation Report window (in this case it will be automatically opened). You will see there are nodes only with width 1, in those nodes go to properties and change the bus width to 4 in your case. I should say this bus width should be adjusted in the simulation report window, not in the *.vwf window.