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Hi,
I was doing simulation with Quartus generated AXI4 bfm in VCS. The script I used to run the simulation is generated by using the Quartus tool (version 23.4.0). While running the simulation, after compilation of all modules I'm getting a DPI import function/task error. I'm posting the error message below:
I checked installation paths and libraries for this function but couldn't find anything related to this file. The input I got from others is like some ".c" file describing this function is missing and that is the cause for this error. For the simulation I'm only using Verilog and System Verilog files and no C files are used. I checked the installation paths, libraries etc. but cannot find any C file. So, what should I do to fix this issue?
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Hi Dins,
Attached the design example script file.
Make sure line 14:
export QUESTA_MVC_GCC_LIB=${MENTOR_VIP_AE}/common/questa_mvc_core/linux_x86_64_gcc-6.2.0_vcs
Make sure included line 30:
export LDFLAGS="-L ${QUESTA_MVC_GCC_LIB} -Wl,-rpath ${QUESTA_MVC_GCC_LIB} -laxi4_IN_SystemVerilog_VCS_full_DVC "
and line 37-42:
$MENTOR_VIP_AE/common/questa_mvc_svapi.svh \
$MENTOR_VIP_AE/axi4/bfm/mgc_common_axi4.sv \
$MENTOR_VIP_AE/axi4/bfm/mgc_axi4_monitor.sv \
$MENTOR_VIP_AE/axi4/bfm/mgc_axi4_inline_monitor.sv \
$MENTOR_VIP_AE/axi4/bfm/mgc_axi4_slave.sv \
$MENTOR_VIP_AE/axi4/bfm/mgc_axi4_master.sv \
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Hi,
Probably have to contact the VCS vendor to get the shared library and specify the path of the shared library for VCS.
For example like Questa simulator will use gcc folder on DPI call.
Thanks,
Sheng
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Hi,
Do you have any further concern or consideration on this thread?
Thanks,
Best Regards,
Sheng
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Hi,
I contacted VCS vendor, and they checked the shared library path that I have given, and it was correct, and they also tried some possible solutions, but it didn't work. They informed me that some ".c" file describing this function (dvc_axi4_initialise_SystemVerilog) is missing and that is the cause for this error. But I failed to find any such ".c" file in libraries. I'm only getting error with the AXI4 BFM IP in Quartus Tool, I can do simulation with other IPs of Quartus in VCS without any issues.
Thanks, and regards,
Dins
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Hi Dins,
Have you got any problem with the axi4 deign example stated in this document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/mentor_vip_ae_usr.pdf
Make sure follow the steps stated for vcs simulation.
May be try regenerate that particular IP as well.
Thanks,
Sheng
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Hi ShengN_Intel,
I didn't get any problem with simulating axi4 design example, and I have followed the same steps as per the document and even tried regenerating the IP as well but getting the same error. I have given the same library paths given in the design example in my design.
Trying all possible ways to fix this issue. Shall I need to define this function (dvc_axi4_initialise_SystemVerilog) anywhere?
Thanks, and regards,
Dins
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Hi,
Possible provide your script for taking a look?
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Hi ShengN_Intel,
I'm attaching my script files as txt files for your reference, please have a look.
Thanks, and regards,
Dins
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Hi Dins,
Attached the design example script file.
Make sure line 14:
export QUESTA_MVC_GCC_LIB=${MENTOR_VIP_AE}/common/questa_mvc_core/linux_x86_64_gcc-6.2.0_vcs
Make sure included line 30:
export LDFLAGS="-L ${QUESTA_MVC_GCC_LIB} -Wl,-rpath ${QUESTA_MVC_GCC_LIB} -laxi4_IN_SystemVerilog_VCS_full_DVC "
and line 37-42:
$MENTOR_VIP_AE/common/questa_mvc_svapi.svh \
$MENTOR_VIP_AE/axi4/bfm/mgc_common_axi4.sv \
$MENTOR_VIP_AE/axi4/bfm/mgc_axi4_monitor.sv \
$MENTOR_VIP_AE/axi4/bfm/mgc_axi4_inline_monitor.sv \
$MENTOR_VIP_AE/axi4/bfm/mgc_axi4_slave.sv \
$MENTOR_VIP_AE/axi4/bfm/mgc_axi4_master.sv \
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Hi ShengN_Intel,
I have done the suggested changes. I haven't added monitor files before in my file list. While adding those files and paths as per the suggestion, the issue is fixed and able to run the simulation.
Thanks for your help.
Thanks, and regards,
Dins

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