Missing clock assignment warning

Altera_Forum · ‎04-29-2015

Hello,

in a Cylone V SOC project under Quartus 14.0 I get the following message from the Linker:

Warning (332060): Node: clk50a was determined to be a clock but was found without an associated clock assignment.

The Project contains a .sdc file with the following constraint:

create_clock -name {clk50a} -period 20.000 -waveform { 0.000 10.000 }

Any idea what I forgot to do?

Altera_Forum · ‎04-29-2015

Try:

create_clock -name {clk50a} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk50a}]

Otherwise you create a clock named clk50a to be used for timing analysis, but you don't bind it to any physical signal.

To be clearer, in general you define

create_clock -name {myclk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk50a}]

and then use myclk to analyze this clock net.

Altera_Forum · ‎04-30-2015

Thank you, Cris72.

It works, the message doesn't appear any more.