Vhdl 2008

[Altera_Forum]

I have recently started using the basic new features of VHDL 2008, and they compile fine in my version of Aldec Active HDL, but do not in Quartus. For example, the basic process: 

 process(MCLK,HRST) begin if (HRST = '1') then  reg <= '0'; elsif rising_edge(MCLK) then  reg <= input; end if; end process;  can be rewritten in VHDL 2008 as:  process(MCLK,HRST) begin if HRST:  reg <= '0'; elsif rising_edge(MCLK) then  reg <= input; end if; end process;  there are several enhancements in VHDL 2008 to reduce verbosity; and I am just trying to find a thread, white paper, or link somewhere that explicity states the VHDL 2008 supported features in Quartus 10. What would be nice is a app note by Altera that maybe takes one of Jim Lewis Synthworks white papers and elaborates on whether those features in VHDL 2008 are covered in Quartus 10.   Thanks, James

[Altera_Forum]

are you sure you dont need the "then" at the end of an if? I thought you had to use the new conditional operator to convert std_logic to a boolean: 

 if ?? HRST then  ..etc  But anyway, the VHDL 2008 supported features are in the quartus manual 10, section 9-10 - VHDL 2008 Support.  As copied from the manual:  The Quartus II software supports the following VHDL 2008 functions: &#9632; Block comments &#9632; Simplified sensitivity lists &#9632; Extensions to generate &#9632; Matching case statement &#9632; Matching equality/inequality operators &#9632; Enhanced bit string literals &#9632; Unconstrained elements in arrays  So nowhere near the full list!

[Altera_Forum]

When using a conditional in an IF statement, the ?? is not required. From the Doulos website: 

 """VHDL-2008 introduces a new operator, ??. It ’s called the condition operator and it converts a STD_LOGIC expression to a BOOLEAN one: '1' and 'H' are considered TRUE and everything else FALSE. (It also converts BIT to BOOLEAN .) So you can now write this:  if ?? A and B then  ...  or, even better ...  In certain circumstances, ?? is applied implicitly. The condition expression of an if statement is one of those. So you can indeed now write:  if A and B then  ..."""    Technically, in my code that I initially listed, I left out the  THEN in the line:  if HRST then:  I had the THEN statement in my code, just didn't copy it. This compiles fine in Aldec HDL where VHDL 2008 is checked  as the language version.   I am trying to find out if Quartus needs the ?? or can discern that that the bit literal should be TRUE.

[Altera_Forum]

Given the supported features, no it doesnt. 

 Im sure Ive accidently left std_logics without an = in some recent code, and it didnt work.  Until it has full 2008 support, it might be safer to stick with 93 for now.

[Altera_Forum]

On a similar note: 

 Does the Altera Modelsim support VHDL-2008? Can't find any mention of it in the Modelsim docs.

[Altera_Forum]

Not in any useful capacity. It has the VHDL 93 version of the fixed point libraries, but thats about it. Quartus has better 2008 support than Modelsim. Apparently, Almost full VHDL 2008 support for modelsim comes with modelsim 6.7 and 6.8

[Altera_Forum]

Thank you. Tried taking advantage of some of the cleaner syntax for base specifiers in constants and it took me longer than I care to admit to realize that this boiled down to VHDL-2008 support.

[Altera_Forum]

Based on my experiment, I found out Quartus II 14.x does not support hierarchical signals. Can anyone confirm this? Thank u

[Altera_Forum]

--- Quote Start ---  Based on my experiment, I found out Quartus II 14.x does not support hierarchical signals. Can anyone confirm this? Thank u  --- Quote End ---    I can confirm this. But why would they want to support them? they are meant for simulation only.

[Altera_Forum]

Can I use hierarchical signals to port out nets / signals in the lower level? Is there other easy way (s) to do that in VHDL. For example, I have three levels in my design. Instead of carrying large number of IO through hierarchy, I can use hierarchical signals to port them to the top level for board level debugging? Thank u

[Altera_Forum]

No. You will need to bring them to a pin.

[Altera_Forum]

Thank u. I understand now

[Altera_Forum]

@waiyoug, for simulation yes, for synthesis into the actual FPGA, no. Synthesis tools need to see the wires that must be routed through the design. And many times there are more signals you want to see for board level debugging than you have pins. So you need additional tools to help you automate multiplexing or scan enabling pins.  

 FYI, ModelSim 10.3 completely supports VHDL-2008 with most of the work completed in ModelSim 10.2. See https://verificationacademy.com/courses/vhdl-2008-why-it-matters.  Dave

[Altera_Forum]

Thank u all. I understand now.

[Altera_Forum]

Does Quartus II 13.1 support VHDL-2008 unconstrained array elements? The Template generator has example unconstrained array constructs and from Tricky's post (in 2010!) I thought 13.1 would support this feature. However, when I try to use them in a design I get: 

 "Error (10294): VHDL Type Declaration error at fir_pkg.vhd(30): element type for array type cannot be unconstrained"  :-(  As the project uses a Cyclone III I need to use a version of Quartus II that supports this device. From looking at the supported devices for the various versions, it looks like 13.1 is the last version to support Cyclone III.

[Altera_Forum]

Did you turn on VHDL 2008 in the compile settings? 

partial 2008 support has been in since about V10

[Altera_Forum]

No...that would probably explain it! 

 Thanks.

[Altera_Forum]

Does Quartus II have support yet for the VHDL-2008 unary 'and', 'or', and 'xor' operators? I just tried to use them on my (Quartus II 13.1) project and it choked on me. Possibly just a syntax error, but I didn't want to spend the time trying to figure it out just to find that the tools can't do that. 

  signal interrupts_in : std_logic_vector(7 downto 0); signal interrupts_out : std_logic; ... interrupts_out <= or interrupts_in;

[Altera_Forum]

The help file says no 

http://quartushelp.altera.com/13.0/mergedprojects/hdl/vhdl/vhdl_list_2008_vhdl_support.htm

[Altera_Forum]

--- Quote Start ---  Can I use hierarchical signals to port out nets / signals in the lower level? Is there other easy way (s) to do that in VHDL. For example, I have three levels in my design. Instead of carrying large number of IO through hierarchy, I can use hierarchical signals to port them to the top level for board level debugging? Thank u  --- Quote End ---    Modelsim can use VHDL-2008 to hierarchically access signals and variables (a useful feature when filling simulation memory).  Quartus does not support VHDL-2008 hierarchical access, but you can do exactly the same thing using the SignalTap II Logic Analyzer.  Cheers, Dave  PS. Oops ... I hit reply to what I thought was the latest message, but it was just the last message on the page ... ah well, its still a valid response, so I'll leave it here.

[Altera_Forum]

Improved 2008 support should be coming in quartus 15.1 (might be just in prime though)