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Mixed blocking and non- with always@ ?

Honored Contributor II



According to ieee.1364 9.2.1: 

“A blocking procedural assignment statement shall be executed before the execution of the statements that follow it in a sequential block (see 9.8.1)” 

and 9.2.2: 

“The nonblocking procedural assignment allows assignment scheduling without blocking the procedural flow.” 


The basic is that for blocking =, compiler calculate a dependency graph first, then simplify to combinational logic; for => it is simultaneous assignment. 

Just as ieee C++ spec doesn’t stipulate how vtable is to laid out (as there are IA64 and MSVC ways to do that), the 1364 spec lacks further restrictions. 

1) Conflict: if Reg A is being assigned in an always block in both categories 

a. First among blocking =’s, then among =>’s, how to resolve? 

b. First among =>’s, then =’s, how? 


I know that for a) case, Quartus basically accept that, but would prohibit any further blocking assignment. Is it a norm for mainstream verilog compilers? 

2) There is a question that for 9.2.1 =’s, because it is defined to be sequential, it somehow suggest the existence of clocks, and indeed# n delay can be added for simulation, and in fact some document suggest that maybe a decade ago there were tools also adding clock delays for# n into synthesis, but that requires knowledge of the specific clock design. I could not find definitive clarification in IEEE standards on this. If, for some ill-define =’s statements, assignment for registers unavoidably require adding delay to ensure correctness. Is there any authoritative source on this? 



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4 Replies
Honored Contributor II

Verilog is defined as a language with bahavioural features. Things work as specified in the LRM when the verilog language is simulated. 


Synthesizers (compared to compilers) take the Verilog and convert it to gates and registers - and they will usually specify the templates they accept for various hardware elements in their documentation (Quartus does). This means that not all of the Verilog language is acceptable to a synthesisor. But it is not Verilog LRM job to specify how synthesisors work.  


I think you are probably coming at this from the wrong end. There will always be far more verilog features that synthsis tools will never accept - Verilog is also meant to be a modelling language, able to model hardware at an abstracted level.  


As a rule of thumb - only use non-blocking assignments inside always blocks, until you understand the consequences of using blocking.# n delays will never be synthesisable (as no circuit exists to allow a specific time period delay to a signal)
Honored Contributor II

“they will usually specify the templates they accept for various hardware elements in their documentation (Quartus does).” 

“Verilog is defined as a language with bahavioural features” 


According to this, does it in any way suggest that there is NO LOWER/UNDERLYING standard for how verilog is synthesized, which is probably understandable since companies might implement proprietary gate/logic units.  

I wonder if there had been any attempt to standardize synthesizer implementation, or perhaps all unsuccessful because this is close to physical level so it might change as device technology advances?
Honored Contributor II

FPGA technologies are roughly the same, but the code the accept is different. Then you have Asic technologies that are different again (there are similarities, but again differences too). 

Afaik, VHDL (and likely verilog) was not originally meant as a synthesisable language. It was originially intended to model digital circuits (VHDL standardised in 1987, Verilog 1995). Then vendors started to support the languages for synthesis. 


Rather than trying to understand the language, it is much better to understand the technology first. Then from there, you understand how to build the circuits with HDL, then over time you'll probably learn how the language works.
Honored Contributor II

I see, thanks a lot.