Mixed verilog and block schematic simulation ? Missing Libraries?
I'm so very frustrated with Quartus, I don't know where to begin other than to say the integration between Quartus and ModelSim absolutely sucks. Quartus seems to be able to launch ModelSim, but falls flat on its face beyond that. Shame on Altera for not doing a better job with this.
I have design that is a mix of Verilog and block schematics. The design compiles successfully with no errors or warnings. So I click on the RTL simulation button and get a screen full of fail. None of the bdf files made it to ModelSim. So I went back and manually created Verilog files from the bdf files and tried again. Still fails. So I created a manually create a project and put all my project verilog files in it. This created a massive minefield which I've been fighting for the last couple of days. Here's a list of problems: The first problem is Quartus's inability to make bdf files available to ModelSim automatically. Maybe there's a way to do this, but I've not found a way yet. The second problem is that my design is split over several pages. I've used the lpm_ff megafunction on a couple of pages. Quartus generated verilog files for the devices, but for some reason it used the same instantiation name for each of the devices (lpm_ff_0). So there's two pages of schematics competing with each other over who owns lpm_ff_0 file. Any ideas how to fix this so that each page gives the device(s) a unique instantiation name? (btw, the schematics do have unique names for each device, but Quartus doesn't use them when creating the verilog files for the megafunction.) The third problem I discovered is when I decided to give up on the RTL simulation which refuses to run and went to gate simulation. I clicked the gate sim button and the vo file did load, but it failed due to missing libraries. WTF? If I specified a device and HDL language, why is it not finding the appropriate libraries? How do I fix this?