Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Mixer II operation



I have some problems to understand how the Mixer II IP works. I have in my system the following video chain:

CVI->Clipper->Deinterlacer->Frame Buffer->Mixer->CVO

I'm using a PCIe endpoint interface for the real-time configuration. The Mixer has a background resolution of 2560x1024. The Frame Buffer is connected to a DDR3 memory.

The input resolution is 1280x1024 and Mixer offset X and Y are set to 0.

In order to simulate the system I first set the Mixer Go bit to '1' and after send my video frame.

The system is created using Quartus Prime 16.1 and for the simulation I'm using QuestaSim 10.4d.

When I send a video frame, the video flows from the input towards the output, but the Mixer how does it work? It first send the background data and after the active video? 

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2 Replies


As I understand it, you have some inquiries related to the Mixer II IP in simulation. To ensure we are on the same page, would you mind to further elaborate on the specific issue that you are observing? Probably some screenshots of your simulation issue will be helpful for better understanding.

For your information, to facilitate the debugging, you can start with simple design ie TPG -> CVO, then slowly add more modules to help narrowing specific issue location.

Please let me know if there is any concern. Thank you.

Best regards,
Chee Pin



As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.