I'm working thru verifying the IP for UniPHY DDR3 for my Stratix IV Device.
In particular, I'm trying to get the numbers for the Board parameters section of the IP and am working on filling out the Board-skew-parameter-tool-v1.0.xlsm using Hyperlynx to analyze our ODB Package.
I was able to easily get the trace delay numbers for each of the DQS Groups (DQ, DM, DQS_P/N) however, I'm not sure where to get the trace delay numbers for CK/COMMAND/ADDRESS Pins to DIMM/Device 0.
Does this trace delay number represent the total trace delay of each net? or is it just the segments leading up to the first DDR3 Chip? if it is just the segments leading up to the first DDR3 chip from the controller, how can I easily extract that segments trace delays from the ODB+ Files using Hyperlynx?
Thanks for your help.
As the tool states, it's the delay from the FPGA ball to the first DIMM or device, like the highlight in your screen shot. If you were able to obtain the values for the DQ/DQS signals, I would think getting the trace lengths for the others would be no different, either in Hyperlynx or whatever board layout tool you use.
However, also note that this tool is not designed for Stratix IV, so I don't know if the numbers returned will be of any help in filling in the memory IP parameters for your design. You might have to manually run the calculations using the correct formulas in the UniPHY IP user guide.