I have a firmware project that was originally done in Verilog, and is still supported in that language. I am working on a variant, and would like to use some existing code that is in VHDL. Although I have the complete source, I would prefer to instantiate the VHDL directly. Some of the models, particularly the processor, would be challenging to port - and take a long time on top. I know this can be done in Xilinx tools by dropping a verilog module declaration with matching ports into the design, and letting ISE figure out the mapping, but I don't know if the same method works in Quartus. My goal is to have a single "top level" VHDL module that instantiates all of the sub modules written in VHDL into the actual top level verilog file. Also, is there an Altera document that discusses mixed language synthesis? Thanks!
