ModelSim Altera SE 10.1e - Error with gate-level sim and test bench parameters

[Altera_Forum]

I have a generic Verilog HDL component that accepts up to two optional parameters. Everything synthesizes and the RTL simulations work as expected. The problem is, I can't run a gate-level simulation in Modelsim, because the module is already placed and routed using the specified default parameters. The error message in ModelSim Altera SE 10.1e is "** Error: (vsim-3006) <filename>: Too many inherited module instance parameters." 

 The only solution I am aware of is to update the parameter defaults inside the top level module and recompile each time. Is there a simpler or faster workaround where I can test multiple instances to check different parameter settings? My top level module is the DUT and I have the test bench included in the project files to compile.  Thanks,  J

[Altera_Forum]

Why are you running a gate-level sim? Most users have gotten away from that completely and rely on RTL and static timing analysis. I'm not sure what a gate-level sim will tell you besides maybe a synthesis bug? 

In larger/newer devices, you can't even run a timing sim and I don't believe you can do gate-level either. But in the older ones where you could, I thought you could write out a simulation model post-synthesis, which would save the actual fit time for each permutation of the parameters.