Hello all,
This is to request an improvement to ModelSim Altera edition. We are glad that the tool now support mixed simulation, thak you. Would it be possible that in the near future the tool also supports SystemVerilog assertions ? This would be a great help. Thanks.Link Copied
This is a public forum not read by altera. You need to raise a my support ticket for enhancement requests.
For more complete information about compiler optimizations, see our Optimization Notice.