ModelSim EDA Gate Level Simulation...

Altera_Forum · ‎03-27-2012

Hi,

I premise, I'm new to ModelSim simulation tool....so

when I try to start an EDA gate-level Simulation (using Modelsim as EDA tool) from Quartus II...I find a pair of errors in ModelSim transcript window:

//----------------------------------------------------------------------------------------

vcom -93 -work work {single_cell_top_2_900mv_85c_slow.vho}

# Model Technology ModelSim SE vcom 6.5c Compiler 2009.08 Aug 27 2009

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package vital_timing

# -- Loading package vital_primitives

# -- Loading package dffeas_pack

# -- Loading package altera_primitives_components

# -- Loading package stratixiv_atom_pack

# -- Loading package stratixiv_components

# -- Compiling entity single_cell_top

# -- Compiling architecture structure of single_cell_top

#

# vcom -93 -work work {C:/One_Sol_Cell/sol_cell_tb.vhd}

# Model Technology ModelSim SE vcom 6.5c Compiler 2009.08 Aug 27 2009

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Compiling entity sol_cell_tb

# -- Compiling architecture arch of sol_cell_tb

#

# vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /single_cell_top=single_cell_top_2_900mv_85c_vhd_slow.sdo -L altera_mf -L altera -L lpm -L sgate -L stratixiv_hssi -L stratixiv_pcie_hip -L stratixiv -L gate_work -L work -voptargs="+acc" sol_cell_tb

# vsim +transport_int_delays +transport_path_delays -L altera_mf -L altera -L lpm -L sgate -L stratixiv_hssi -L stratixiv_pcie_hip -L stratixiv -L gate_work -L work -voptargs=\"+acc\" -sdftyp /single_cell_top=single_cell_top_2_900mv_85c_vhd_slow.sdo -t 1ps sol_cell_tb

# ** Note: (vsim-3812) Design is being optimized...

# ** error: (vopt-2216) failed to find instance 'single_cell_top' .

# ** error: (vopt-1943) command line sdf instance pathname "/single_cell_top" cannot be resolved.

# Optimization failed

# Error loading design

# Error: Error loading design

# Pausing macro execution

# MACRO ./single_cell_top_run_msim_gate_vhdl.do PAUSED at line 52

//----------------------------------------------------------------------------------------------

Do you know something about that???

Thanks

Regards