ModelSim Incorrect PLL output frequency

[Altera_Forum]

I have a PLL in my design that was generated using the MegaWizard tool. When I simulate my design in ModelSim, the output frequency of the PLL is not correct. I can modify the output frequency using the MegaWizard tool and can see the ModelSim frequency also change, but the value is still not correct. Here are a few examples: 

 Desired frequency : Observed frequency 120MHz : 20MHz 100MHz : 16.67MHz 5MHz : 840kHz 25MHz : 4.2MHz  The observed frequency seems to always be about 16.67% of the desired frequency.   I see this message in ModelSim printed during simulation:# Note : Cyclone IV E PLL locked to incoming clock# Time: 312 Instance: sidewinder2_red_fpga_tb.sidewinder2_red_fpga_top_inst.pll_clk_25_inst.altpll_component.cycloneiii_pll.pll3  My Quartus version is: 32-bit Version 12.1 Build 177 11/07/2012 SJ Full Version ModelSim is: Altera Starter Edition 10.1b Revision 2012.04, Apr 27 2012  My target device is Cyclone IV E, EP4CE15U14I7.  Anyone have any ideas? Does it matter that ModelSim is using a CycloneIII PLL module within the altera_mf.v file??

[Altera_Forum]

Did you already measure the period of the Pll input clock? 

 it looks like your input clock is 1/6 of the period.    --- Quote Start ---  # Note : Cyclone IV E PLL locked to incoming clock # Time: 312 Instance: sidewinder2_red_fpga_tb.sidewinder2_red_fpga_top_i nst.pll_clk_25_inst.altpll_component.cycloneiii_pl l.pll3  --- Quote End ---    That's ok, I think. I have also a design, where Modelsim gives me the same comment for a Cyclone IV (... /TopFpga_inst/IClockManager_inst/altpll_component/cycloneiii_altpll/m5).

[Altera_Forum]

--- Quote Start ---  Did you already measure the period of the Pll input clock?  it looks like your input clock is 1/6 of the period.   The input reference clock is defined as 19.2MHz in the MegaWizard tool. I verified that the reference clock in ModelSim is indeed 19.2MHz.

[Altera_Forum]

What period do you get for the input clk in Modelsim? 

 Are you sure, the correct clock is going to the Pll?   Did you try deleting the "work" folder generated by Modelsim? Sometimes it happens that the folder is not up-to-date.

[Altera_Forum]

The input clock, monitored within the PLL instance itself (inclk0), is ~52nS. 

 I tried deleting the work folder per your suggestion. Unfortunately my results are the same.

[Altera_Forum]

What have you set the Modelsim resolution to? 

 It needs to be ps with PLLs, often things default to ns.   I've been caught with this a couple of times but from memory most of the time things just don't work if this is the problem.   Nial.