ModelSim Newbie

[Altera_Forum]

Hello All, 

 I've just started learning Verilog and as a part of the process i decided to test the testbenches with Verilog PE Student Edition 6.4 . When i compile a verilog file ,it compiles without any error but i have no object file after that! How can i simulate the code? __________________________________________________________________ module stimcrct;  reg A,B,C;  wire x,y;  circuit_with_delay cwd(A,B,C,x,y);  initial  begin  A = 1'b0 ; B = 1'b0 ; C = 1'b0;  # 100  A = 1'b1 ; B = 1'b1 ; C = 1'b1;  # 100 $finish;  end endmodule  module circuit_with_delay (A,B,C,x,y);  input A,B,C;  output x,y;  wire e;  and# (30) g1(e,A,B);  or # (20) g3(x,e,y);  not# (10) g2(y,C); endmodule _______________________________________________________________  Please HELP !!!  Best Regards

[Altera_Forum]

So you are not using QuartusII for your compilation?

[Altera_Forum]

--- Quote Start ---  So you are not using QuartusII for your compilation?  --- Quote End ---    No. I've only started learning Verilog.

[Altera_Forum]

ModelSim has tutorials, they offer an effective way to learn the operation to my opinion.

[Altera_Forum]

When you compile your Verilog design in ModelSim (using the vlog command), it will create a work library that you will need to simulate from using the vsim command. 

 You can refer to the user guides that came with your installation on how to do this.

[Altera_Forum]

Modelsim has a graphical user interface for a lot of things but I prefer using script files like this: 

 vlib work vlog ../hdl/file1.v vlog ../hdl/file2.v ... vsim -L <library_name> -do wave_all.do work.top log -r /* run -all  whereas wave_all.do is the wave file generated with the waveform view. The script is then run from the ModelSim console with do <scriptfilename>, i.e. do test_all.do