Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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sharing designs without sharing source files

Altera_Forum
Honored Contributor II
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I wish to share a sub design without sharing the vhdl source files in order to protect my IP. The sub design is hierarchical and has generic parameters which allows for configuration of the complete design on a higher level.  

 

I've tried exporting and importing partitions but I ran into problems with the parameters and I/O registers.  

 

Is there another way to achieve the goal (apart from becoming an Altera IP provider)?
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Altera_Forum
Honored Contributor II
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I don't believe so. People have used .vqms and partitions for this type of thing, which is easier since you don't have to set up a license for the end customer(and not as well protected, because of that). But both of those methods provide post-synthesized netlists, so you will lose all parametrization and force a specific synthesis(i.e. the end user couldn't re-target a differnet family).  

The only thing I can think of that might be worth googling is "obfuscation". Basically this is an algorithm that re-names all of your nets, registers, parameters, etc. to completely unintelligible names. So someone could still look at the RTL, but it's much, much more difficult to read. I don't know if there are any free tools out there for this, but I believe Altera used to do it and I've heard of other companies doing it, so wouldn't be surprised if something like that existed.
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Altera_Forum
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