Hi,
Sorry for my lame question, I'm new to this world... I used to use Quartus Simulator to simulate my VHDL design, it is easy to use, but the feature is limited. So I try to use ModelSim Altera Edition, it is complex and hard to use (I think :D ). Unlike Quartus Simulator, I can't find how to create random value for my input signal. Please help me how to solve this problem... Any kind of help will be appreciated... Thanks...链接已复制
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In Modelsim, you have to write your own testbench to stimulate your design, so you will have to generate random numbers in VHDL.
There are 2 ways of doing this: 1. Use a linear feedback shift register. have a look at http://en.wikipedia.org/wiki/lfsr 2. There is a random number generator in the ieee.math_real package, a procedure called "uniform". It generates Reals between 0.0 and 1.0 (inclusive I think) and you can use this to generate random integers by scaling between two limits. Here is a procedure I created in a "testbench_tools" package for generating random integers (which can easily be converted to signed/unsigned/slv/ufixed/sfixed):
procedure rand_int( variable seed1, seed2 : inout positive;
min, max : in integer;
result : out integer) is
variable rand : real;
variable val_range : real;
begin
assert (max >= min) report "Rand_int: Range Error" severity Failure;
uniform(seed1, seed2, rand);
val_range := real(Max - Min + 1);
result := integer( trunc(rand * val_range )) + min;
end procedure;
the two seed value must be variables in your testbench. min and max set the limits of the random number generation (inclusive). result is the random number
A testbench usually has no inputs and no outputs (ie. no port declaration), it justs generates the IO for the unit under test. You would not compile a testbench in quartus, and it would not go into the FPGA.
my testbenches usually start like this:
entity my_ent_TB is
end entity my_ent_TB;
architecture test of my_ent_TB is
begin
....
end architecture my_ent_TB;
VHDL supports ALOT of stuff that you cant compile in quartus, which is intended exactly for simulation. For example, to generate a clock, you can do this: clk <= not clk after 10 ns; --a 100MHz clk. and for specified inputs: input <= '1', '0' after 1 us, '1' after 2us, '0' after 5us ; --etc. or for more complicated things (like random number input procedure above): assume input_slv is an 8 bit bus:
process
variable seed1, seed2 : positive := 1587437; --any number will do. Different seed value changes the sequence.
variable input_int : integer;
begin
wait until rising_edge(clk);
rand_int(seed1, seed2, 0, 255, input_int);
input_slv <= std_logic_vector( to_unsigned( input_int, 8));
end process;
