ModelSim does not see the wires

[Altera_Forum]

I draw a simple circuit in which the name on the wire is connecting the two components. 

Instance inst has output to the wire called w1  And inst2 has an input with a wire, called w1.  Next, we use the tools available in the Quartus:  compile  get netlist  create a test bench through the Start Test Bench Template Writer  ModelSim runs through the Gate Level Simulation button  Compile a test-bench in ModelSim  Run the simulation  By default, the Test Bench Template Writer  creates i1: project_name PORT MAP (...)  So ...  In the simulation all input ports and output can be seen normally. But the w1 connection can not be found in the ModelSim i1 branch.  Does not ModelSim see the internal wires?

[Altera_Forum]

Is it true that the schematic can be tested only through the Gate Level Simulation button?

[Altera_Forum]

yes, or you could convert it to HDL to do an RTL simulation

[Altera_Forum]

Yet the question remains about the internal signals are not presented in the ports.  

The vho file contains only generated signals. In the vht generated file internal signals are absent.  And accordingly they are not in the ModelSim instances list. It's uncomfortable.

[Altera_Forum]

I'm creating a project using a hierarchical schematic.  

In a previous post I complained about the inability to monitor the internal signals. Here's one solution... I convert all the schematic files in the VHDL code. All schematic files were excluded from project since the error: Error (12049): Can't compile duplicate declarations of entity "zzz" into library "work" After compiling  The testbench is generated automatically by PROCESSING/START/START_TEST_BENCH_TEMPLATE WRITER. For button RTL simulator automatically starts the ModelSim.  In the hierarchical tree i1 shows all the internal signals (the names of the wires). For the next iteration, I restore schematic and remove VHDL from project, I am doing the necessary changes, create new VHDL files  and start a new simulation. Is this the only way to work with a hierarchical schematic design or are there ways to automate it?

[Altera_Forum]

Best thing to do is to use VHDL from the start.

[Altera_Forum]

Thank you for a little bit. 

But I am a little unclear 8O) Is it possible to get some explanation?

[Altera_Forum]

Dont use schematic files ever. Write HDL yourself.

[Altera_Forum]

Is there a unique solution?