Re: ModelSim -> Cannot open `include file

Altera_Forum · ‎10-16-2011

Hy everyone,

I am working with ModelSim 6.4a. I created two .v files which "included" the other .v file.

one of my .v files :

module My_CMD_FSM(

//input

cmd_fsm_clk,

cmd_fsm_rst_n,

init_done,

Rd_WrN,

cmd_fsm_iaddr,

cs_state,

wren,

);

`include "ddr_par.v"

`define endOf_tRP cs_clkcnt == NUM_CLK_tRP

`define endOf_tRFC cs_clkcnt == NUM_CLK_tRFC

`define endOf_tMRD cs_clkcnt == NUM_CLK_tMRD

`define endOf_tRCD cs_clkcnt == NUM_CLK_tRCD

............

(so on)

Where ddr_par.v is a code file with multiple frequently used parameter.

ddr_par :

module param ();

//---------------------------------------------------------------------

// DDRAM mode register definition

//

// Burst Length

parameter Length_1 = 3'b000;

parameter Length_2 = 3'b001;

parameter Length_4 = 3'b010;

parameter Length_8 = 3'b011;

// Burst Type

parameter Sequential = 1'b0;

parameter Interleaved = 1'b1;

// Latency Mode (CAS Latency )

parameter Latency_2 = 3'b010;

parameter Latency_3 = 3'b011;

// Operation Mode

parameter Standard = 2'b00;

// Write Burst Mode

parameter Programmed_Length = 1'b0;

parameter Single_Access = 1'b1;

............

(so on)

I got error message : cannot open `include file ddr_par.v

After doing some searching , I found that :

1. global parameter can't be used (i don't really understand how it works)

2. change the directory of "include" can solve the problem

so i change it to : 'include "C:/SDRAM_controller_ModelSim_test/ddr_par.v"

And I don't get above error anymore but the parameter is still cant be read.

Error Message : undefined variable .... etc (since i got all of the variables on the ddr_par.v)

Thank you in advance,

Yuyex:o

Altera_Forum · ‎10-16-2011

In the ddr_par.v file, you've put the parameters inside a module definition. So, they're only visible inside it.

If I understand what you want to do, you just need to remove the "module param();" and "endmodule" lines from the ddr_par.v file

Or put in another way: `include directive is literaly replaced by the code from the ddr_par.v file. So, think how your code looks when the `include is processed.

Altera_Forum · ‎10-16-2011

Thank you for your reply rbugalho,

At the beginning , I did what you said to me (ddr_par.v without module-endmodule), but i got error message : global declarations are illegal in verilog 2001 syntax.

From other forum , there's someone who said that most of verilog source code have module-endmodule. I know it but i don't think "this parameter file" needs it (am I wrong?) , but it is worthy to try, so I added module-endmodule into ddr_par.v .

And the idea of changing the directory of 'include is also comes from another forum too, but it didn't solve my problem.

Thank you in advance,

Yuyex:o

Altera_Forum · ‎10-18-2011

Two things may help further -

1. if you do not specify a path to the included file, then modelsim compiler assumes the file is located in the same folder from which you are running the compile. You can specify an include folder on the command line as - vlog module_to_be_compiled +incdir+C:/SDRAM_controller_ModelSim_test

2. Global declarations are illegal in Verilog 2001 syntax - I haven't seen this error myself, but I can think of a few pointers. Take it for what its worth.

2.a. How are you using hte parameters? Are you using the parameters in the same module as you have the `include statement? Or are you using those parameters in blocks lower in the hierarchy?

2.b. Also, something to look for is if you are using parameters as variables e.g. assign Length_1 = 3'd4;

2.c. Maybe your problem is not from the parameter declaration but the `define declaration after the code is successfully compiled. What if you enclose the argument to the defined term as (cs_clkcnt == NUM_CLK_tRP)

Altera_Forum · ‎10-19-2011

Thank you for your reply , fpgabuilder.

I have solved the path issue. Seems like there can't be any "space character" in the file data path.

I thought that I am compiling the file on the "C:/SDRAM_controller_ModelSim_test/" folder , but I compiled the wrong path "C:\Documents and Settings\Yuyex\Desktop\modelsim test1" :eek: (i compiled my backup files .. omG)

Here comes another issue from ddr_par.v which is still confusing me.

Error message :

1. (vlog-2155) global declarations are illegal in verilog 2001 syntax.

2. undefined variable: length_1.

3. 'length_1' already declared in this scope (work).

code (ddr_par.v):

// burst length

parameter length_1 = 3'b000;

parameter length_2 = 3'b001;

parameter length_4 = 3'b010;

parameter length_8 = 3'b011;

....

(so on)I cant use 'define since I still need some selection function on the parameter (at ddr_par.v), such as :

parameter num_clk_read = (mr_burst_length == length_1) ? 1 :

(mr_burst_length == length_2) ? 2 :

(mr_burst_length == length_4) ? 4 :

(mr_burst_length == length_8) ? 8 :

1; // default

From your last reply,

--- Quote Start ---

a. How are you using the parameters? Are you using the parameters in the same module as you have the `include statement? Or are you using those parameters in blocks lower in the hierarchy?

--- Quote End ---

I am using ddr_par.v in all of the other .v files , that's why I have to use 'include in order to reduce the lines number.

--- Quote Start ---

2.b. Also, something to look for is if you are using parameters as variables e.g. assign Length_1 = 3'd4;

--- Quote End ---

I'm using bit expression for this Length _1 since this bits will be sent to "SDRAM Load Mode Register" to initialize the characteristic of SDRAM itself.

Do you mean that it's better to use assign than parameter?

--- Quote Start ---

2.c. Maybe your problem is not from the parameter declaration but the `define declaration after the code is successfully compiled. What if you enclose the argument to the defined term as (cs_clkcnt == NUM_CLK_tRP)

--- Quote End ---

This "global parameter" thing is the problem for now :((

Thank you in advance,

Yuyex:o

Altera_Forum · ‎10-24-2011

is there anyone who can help me ?

I tried to install the ModelSim 6.6 SE , but it still didn't solve my problem ..

Is there any method to applied some parameters into different .v files without 'including it? (like what i did and failed)

Thank you :o

Altera_Forum · ‎10-24-2011

I have seen the user guide from MOdelSim user manual , there's a "grouping files" function.

explanation from the user manual :

you can group two or more files in the compile order dialog so they are sent to the compiler at

the same time. for example, you might have one file with a bunch of verilog define statements

and a second file that is a verilog module. you would want to compile these two files together.

I have grouped the ddr_par.v a .v file and compile them together , but I got 1 error message : no compile information available. the source file may have been edited and saved since the last compile.

I am new to ModelSim, so I'm hoping for your the advice.

Thank you,

Yuyex:o