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ARuss12
Beginner
282 Views

Modelsim 10.1d and UNDEFINED entities internal signals

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Good morning all,

 

This is my first post in this forum, so i apologize in advance if the section is not completely correct.

 

I started recently wih FPGA design, and i am doing some homeworks from my university course in digital electronics. In particular, i am trying to test a circuit with some entities (flip flops, BCD converters, 7 segment display, ecc) with a test bench simulated with Modelsim 10.1d Starter Edition.

 

The problem is that i am not able to see the internal signals of my design. in particular, (see attached pic) i can watch the signals of the top TestBench entity, but not the signals in the inner entities (such as FFs) which appear "undefined" or U in the waveform view. How can i solve this? I already tried to modify the ".ini" file to set:

 

; Turn off optimization for IEEE std_logic_1164 package. Default is on.

 Optimize_1164 = 0

 

Which i saw on the internet can be a problem. But nothing changed. Can you please give me some suggestions? Thanks in advance.

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1 Solution
Vicky1
Employee
121 Views

Hi,

Thanks for the project file.

Please initialize the all the I/os in test bench like below, then Add the internal signals like 'FF1' & 'FF2' in wave window & try to 'run simulation'.

please find the attachment for screenshot.

SIGNAL STOP : STD_LOGIC := '0'; SIGNAL EnDig1 : STD_LOGIC:= '0'; SIGNAL EnDig3 : STD_LOGIC:= '0'; SIGNAL START : STD_LOGIC:= '0'; SIGNAL LED : STD_LOGIC:= '0'; SIGNAL EnDig0 : STD_LOGIC:= '0'; SIGNAL Digits : STD_LOGIC_VECTOR(6 DOWNTO 0):= "0000000"; SIGNAL EnDig2 : STD_LOGIC := '0'; SIGNAL CLK : STD_LOGIC:= '0';

sim.JPG

Regards,

Vicky

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4 Replies
Vicky1
Employee
121 Views

Hi,

Have you initialized the signals in test bench?

clock is not working in attached pic.

Could you provide project file('Project' Menu->'Archive Project') *.qar file for replication?

Regards,

Vicky

ARuss12
Beginner
121 Views

Thanks for your answer! My bad, the pic is too zoomed and the clock looks still, but it's actually toggling. I am attaching the .qar file as requested.

 

I corrected some things but i still see a behavior that i can't understand. In particular, it looks like the internal signals of my entites are not correct if not brought "outside" as output of the top entity simulated in the testbench. For example, the signal "enableFromFF" is istantiated in the top entity "ReactionTimer.vhd". If selected in the object menu and plotted in the waveform, it has a (wrong) behavior. If i put this signal as an output of the entity "ReactionTimer.vhd" and visualize it directly from the testbench entity, it has a different (and correct, as expected) behavior. The only difference is that i acces to this signal INSIDE the entity "ReactionTimer", or as an output from it. See the newly attached pictures that describe this behavior.

 

 

Comparison of the two EnableFromFF signals, seen in the entity and in the testbench (extracted as output)

SignalsComparison.PNG

 

TestBench vs top entity "ReactionTimer"

TestBench_vs_TopEntityReactionTimer.PNG

Vicky1
Employee
122 Views

Hi,

Thanks for the project file.

Please initialize the all the I/os in test bench like below, then Add the internal signals like 'FF1' & 'FF2' in wave window & try to 'run simulation'.

please find the attachment for screenshot.

SIGNAL STOP : STD_LOGIC := '0'; SIGNAL EnDig1 : STD_LOGIC:= '0'; SIGNAL EnDig3 : STD_LOGIC:= '0'; SIGNAL START : STD_LOGIC:= '0'; SIGNAL LED : STD_LOGIC:= '0'; SIGNAL EnDig0 : STD_LOGIC:= '0'; SIGNAL Digits : STD_LOGIC_VECTOR(6 DOWNTO 0):= "0000000"; SIGNAL EnDig2 : STD_LOGIC := '0'; SIGNAL CLK : STD_LOGIC:= '0';

sim.JPG

Regards,

Vicky

View solution in original post

ARuss12
Beginner
121 Views

Ok it seems that the problem is that i used to simulate all the entities (testbench + all the others) and drag the signals from inside the entity. If i drag the signal starting from the testbench, it is all right! Thanks!

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