Modelsim Altera Starter Edition problem

[Altera_Forum]

Hello, 

 I'm a newbie about QuartusII and Modelsim. This is my problem: in my VHDL entity there are eight signals (1bit wide): IN0,IN1,IN2,IN3...IN8 I would like to force their values like a bytes (in decimal or hex values) but when I use Modelsim I can only set their values one bit at a time. I tried to combine them in a but it isn't possible to force a combined signal (Modelsim doesn't do anything when i press FORCE on the combined signal alias). Is it possible to force the eigth values like a single byte? Best regards.

[Altera_Forum]

--- Quote Start ---  Hello,  I'm a newbie about QuartusII and Modelsim. This is my problem: in my VHDL entity there are eight signals (1bit wide): IN0,IN1,IN2,IN3...IN8 I would like to force their values like a bytes (in decimal or hex values) but when I use Modelsim I can only set their values one bit at a time. I tried to combine them in a but it isn't possible to force a combined signal (Modelsim doesn't do anything when i press FORCE on the combined signal alias). Is it possible to force the eigth values like a single byte? Best regards.  --- Quote End ---    using force from GUI is not best way of simulating.  better use testbench (wrap up your design anf force iinputs as you like in code).  alternatively combine all your inputs into one byte to start with.  here is what a testbench may look like:   library ieee; use ieee.std_logic_1164.all; entity test_tb is end entity; architecture a of test_tb is signal clk : std_logic := '0'; signal din : std_logic_vector(7 downto 0) := (others => '0'); component dut port( clk : in std_logic; in1 : in std_logic; in2 : in std_logic; -- etc... dout : out std_logic_vector(7 downto 0) ); end component; begin clk <= not clk after 10 ns; din <= x"02" after 50 ns, x"07" after 70 ns, x"05" after 90 ns, x"01" after 110 ns, x"03" after 130 ns, x"06" after 150 ns, x"08" after 170 ns, x"04" after 190 ns; inst1: dut port map( clk => clk, in1 => din(0), in2 => din(1), dout => open ); end a;