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i have a little problem with my manager input ( W ) i can't find TIME PERIOD for my project ( For W )
( On photo W have constant 1, but in project it have change beatwen 0 and 1 )
So, if someone know how calculate Time period for W, please explaine how u found it
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Without seeing the design or some code, there's no way to know. Can you provide that and more details on what you're expecting?
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Hi,
What frequency are you driving the signal? Is it from testbench or forcing it in waveform?
Regards
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i dont understand ur question :c, but its i a little bit stuoid :3, i try explain what i want:
I have pin W, its enable pin for project Lab3_11, in ModelSim i dont know whitch time i have set for get those lines ( on screenshot ) , so my main problem its which time set for pin W in ModelSim to get those lines ( YA ( my MUX ) have be same with YB( common MUX in Quartus ), but enable pin W ruin me evrething :c )
its when i set W constant = 1
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W is coming from an input pin so its period/frequency would depend on whatever is driving that input from the board, outside the FPGA. There's no info here to determine that.
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Hi,
The issue is still not clear to me. Input W looks like a static input and not a clock. What do you mean when you asked TIME PERIOD for W, in your first post?
As I understand from the block diagrams that you pasted, input W has no effect on output YB. Its acts as enable for output YA only. If W = 1, both the outputs YA and YB behave as a mux. But if W = 0, YA will probably always be 0.
Regards
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W its like enable input
And yep, its 2 mux, YB standart mux, which in quartus, YA its own mux
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Hi,
Your query is application specific, so it depends upon how frequently the higher-level module is going to change the input.
I think for testing purpose, you can just provide any frequency. The outputs should change accordingly.
Regards
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