Modelsim: High Z in Gate Level Simulation

[Altera_Forum]

In my gate level simulation, some of the signals are in High Z state from beginning to end of simulation. It is not happening in RTL level simulation. May i know what are the possible reason can cause High Z and any solution for this issue? thanks

[Altera_Forum]

Check whether you got initialize these signals?

[Altera_Forum]

I have initialized the signals. Any other possible reason to cause this?

[Altera_Forum]

I wonder what "initialized the signals" means? A 'Z' signal can be sourced only from a tri-state driver. Initializing a tristate node is meaningless in my opinion. Registered signals can be initialized, e.g. a register feeding the output enable of a tristate driver, but tristate nodes can't be initialized other than to 'Z', which may be necessary in simulation in some cases. Unitialized signals would show as 'U', driver conflicts as 'X'. 

 If you expect other than 'Z' from a tristate node, you have to determine which driver is expected to drive the node and why it doesn't.

[Altera_Forum]

I don't use any tristate in the design. I found out that the Z is caused by unused bits in internal signals(vector). I have no idea why does modelsim display unused bits in high Z condition.  

 eg. reg [3:0] a ; reg [3:0] b; reg [7:0] result; output reg [3:0] result_truncate;  result <= a * b; result_truncate <= result[7:4];  the signal result[3:0] will be high Z.   How to set the modelsim to display the Z value as zero value?     --- Quote Start ---  Unitialized signals would show as 'U', driver conflicts as 'X'.  --- Quote End ---    from my past experience in using the modelsim, whenever deal with X, it always relate to uninitialized of signal if the X happen in the beginning of the simulation. It uses X instead of U. Besides, X also represents driver conflict when in the middle of simulation.

[Altera_Forum]

--- Quote Start ---  I don't use any tristate in the design. I found out that the Z is caused by unused bits in internal signals(vector). I have no idea why does modelsim display unused bits in high Z condition.   eg. reg [3:0] a ; reg [3:0] b; reg [7:0] result; output reg [3:0] result_truncate;  result <= a * b; result_truncate <= result[7:4];  the signal result[3:0] will be high Z.   How to set the modelsim to display the Z value as zero value?    from my past experience in using the modelsim, whenever deal with X, it always relate to uninitialized of signal if the X happen in the beginning of the simulation. It uses X instead of U. Besides, X also represents driver conflict when in the middle of simulation.  --- Quote End ---    Hi,  as far as I know all highlevel simulator will behave in this way. You have to keep in mind that you are simulating a netlist after synthesis. That means a lot of optimization are done on your design. The simulator indicates with "Z" that the net is not driven anymore. It should be a hint for you to look whether this is ok or not. Alternative the simulator could split the bus and remove all unused bits, but I never saw this behaviour.  Kind regards  GPK

[Altera_Forum]

Could we perhaps see all of your code? That might give a hint.

[Altera_Forum]

Pletz is right. High 'Z' is the simulators way to tell, that the respective bits have been removed in synthesis, because no FPGA output depends on it.