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Modelsim Simulation error

Shainy
Beginner
340 Views

Hi,

I've been trying to simulate an IP core on Modelsim. The IP core I'm using is ALTFP_MULT IP core (floating-point multiplier), with double precision and an output latency of 5(the lowest latency possible). And below is the testbench I created for simulation purposes on Modelsim. The issue is that, as shown in the image, when I try to run this, only a blue line is visible as the output. Really appreciate if someone could kindly help me figure out what's wrong with my testbench/modelsim simulation. Thanks in advance!

[dataa/datab= input data    ||   result= output of the multiplier]

 

`timescale 1 ps / 1 ps
module fpmulttrial_tb();

reg [63:0] dataa, datab;
reg clk;
wire [63:0] result;

fpmult1try UUT( .dataa(dataa), .datab(datab), .clock(clk), .result(result));


initial begin

clk=1;

dataa= 000;
datab= 10.97;
#100

dataa= 7;
datab= 19.97;
#100

dataa= 9;
datab= 109.7;
#100

dataa= 10;
datab= 1.97;
#100

dataa= 4;
datab= 1.7;
#100

dataa= 9;
datab= 19.9797;
#100

dataa= 3;
datab= 9.7;


end

endmodule

0 Kudos
2 Replies
sstrell
Honored Contributor III
306 Views

You're not toggling the clock input in the testbench.

Shainy
Beginner
290 Views

Hi @sstrell ,

Thank you so much for your reply! I tried to toggle the switch, with the following modified code, but still I have the same issue. Is there anything else that I've done wrong or maybe there's anything more I should add?

`timescale 1 ps / 1 ps
module fpmulttrial_tb();

reg [63:0] dataa, datab;
reg clk;
wire [63:0] result;

fpmult1try UUT( .dataa(dataa), .datab(datab), .clock(clk), .result(result));

always

#100
clk= ~clk;

initial begin

clk=1;

dataa= 000;
datab= 10.97;
#100

dataa= 7;
datab= 19.97;
#100

dataa= 9;
datab= 109.7;
#100

dataa= 10;
datab= 1.97;
#100

dataa= 4;
datab= 1.7;
#100

dataa= 9;
datab= 19.9797;
#100

dataa= 3;
datab= 9.7;
#100

$finish;
end

endmodule

 

Thanks a bunch!

 

Best Regards,

Shainy

 

Shainy_0-1631431796785.png

 

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