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Modelsim altera error

Altera_Forum
Honored Contributor II
‎11-30-2010 08:33 PM
2,354 Views

Hi there, 

 

I have quite a few inout ports on the top module. For them to be output, I have declare them as reg. But these ports give me "Illegal reference to net <..>" when I try to run simulation (compilation runs through with warnings). 

 

Help please.
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Altera_Forum
Honored Contributor II
‎12-01-2010 07:23 AM
1,379 Views

 

--- Quote Start ---  

Hi there, 

 

I have quite a few inout ports on the top module. For them to be output, I have declare them as reg. But these ports give me "Illegal reference to net <..>" when I try to run simulation (compilation runs through with warnings). 

 

Help please. 

--- Quote End ---  

 

 

Hi, 

 

can you please post your code. 

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
‎12-01-2010 03:26 PM
1,379 Views

my bad.. sorry. 

 

I have attached a portion of my code below; while running Modelsim Altera, I get the above error. Basically, based on the 4 bit dap_route code, I either loop-back some ports or route to outside CPLD (Max II). 

 

module top_v ( 

 

//DAP1 

inout wire dap1_fs, 

inout wire dap1_sclk, 

input dap1_dout, //input w.r.t CPLD 

output wire dap1_din, //output w.r.t CPLD 

//DAP2 

inout wire dap2_fs, 

inout wire dap2_sclk, 

input dap2_dout, 

output wire dap2_din, 

//DAP3 

inout wire dap3_fs, 

inout wire dap3_sclk, 

input dap3_dout, 

output wire dap3_din, 

 

input [3:0] dap_route 

); 

 

//Instantiating a module 

dap_test_binary dap_call( 

 

//DAP1 

.dap1_fs(dap1_fs), 

.dap1_sclk(dap1_sclk), 

.dap1_dout(dap1_dout), //input w.r.t CPLD 

.dap1_din(dap1_din), //output w.r.t CPLD 

//DAP2 

.dap2_fs(dap2_fs), 

.dap2_sclk(dap2_sclk), 

.dap2_dout(dap2_dout), 

.dap2_din(dap2_din), 

//DAP3 

.dap3_fs(dap3_fs), 

.dap3_sclk(dap3_sclk), 

.dap3_dout(dap3_dout), 

.dap3_din(dap3_din), 

 

.dap_route(dap_route) 

); 

 

//Actual module 

module dap_test_binary ( 

 

//DAP1 

inout reg dap1_fs, 

inout reg dap1_sclk, 

input dap1_dout, //input w.r.t CPLD 

output reg dap1_din, //output w.r.t CPLD 

//DAP2 

inout reg dap2_fs, 

inout reg dap2_sclk, 

input dap2_dout, 

output reg dap2_din, 

//DAP3 

inout reg dap3_fs, 

inout reg dap3_sclk, 

input dap3_dout, 

output reg dap3_din, 

 

input [3:0] dap_route 

); 

 

always @ (*) 

begin 

case (dap_route) 

 

4'b0000: begin //DAP1 (master) looped back to DAP2 

dap1_din = dap2_dout; 

dap2_din = dap1_dout; 

dap2_fs = dap1_fs; 

dap2_sclk = dap1_sclk; 

end  

 

4'b0001: begin //DAP2 (master) looped back to DAP1 

dap1_din = dap2_dout; 

dap2_din = dap1_dout; 

dap1_fs = dap2_fs; 

dap1_sclk = dap2_sclk; 

 

end  

 

4'b0010: begin //DAP1 (master) looped back to DAP3 

dap1_din = dap3_dout; 

dap3_din = dap1_dout; 

dap3_fs = dap1_fs; 

dap3_sclk = dap1_sclk; 

 

end  

 

4'b0011: begin //DAP3 (master) looped back to DAP1 

dap1_din = dap3_dout; 

dap3_din = dap1_dout; 

dap1_fs = dap3_fs; 

dap1_sclk = dap3_sclk; 

 

end  

 

default: begin 

dap1_fs = 1'bz; 

dap1_sclk = 1'bz; 

dap1_din = 1'bz; 

 

dap2_fs = 1'bz; 

dap2_sclk = 1'bz; 

dap2_din = 1'bz; 

 

dap3_fs = 1'bz; 

dap3_sclk = 1'bz; 

dap3_din = 1'bz; 

 

end 

 

endcase  

end  

endmodule  

 

 

//errors 

* Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(41): (vlog-2110) Illegal reference to net "dap2_fs".# ** Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(42): (vlog-2110) Illegal reference to net "dap2_sclk".# ** Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(4http://www.edaboard.com/images/smilies/icon_cool.gif : (vlog-2110) Illegal reference to net "dap1_fs".# ** Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(49): (vlog-2110) Illegal reference to net "dap1_sclk".# ** Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(56): (vlog-2110) Illegal reference to net "dap3_fs".# ** Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(57): (vlog-2110) Illegal reference to net "dap3_sclk". 

 

 

Thanks for your help. 

 

regards
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Altera_Forum
Honored Contributor II
‎12-02-2010 09:53 AM
1,379 Views

 

--- Quote Start ---  

my bad.. sorry. 

 

I have attached a portion of my code below; while running Modelsim Altera, I get the above error. Basically, based on the 4 bit dap_route code, I either loop-back some ports or route to outside CPLD (Max II). 

 

module top_v ( 

 

//DAP1 

inout wire dap1_fs, 

inout wire dap1_sclk, 

input dap1_dout, //input w.r.t CPLD 

output wire dap1_din, //output w.r.t CPLD 

//DAP2 

inout wire dap2_fs, 

inout wire dap2_sclk, 

input dap2_dout, 

output wire dap2_din, 

//DAP3 

inout wire dap3_fs, 

inout wire dap3_sclk, 

input dap3_dout, 

output wire dap3_din, 

 

input [3:0] dap_route 

); 

 

//Instantiating a module 

dap_test_binary dap_call( 

 

//DAP1 

.dap1_fs(dap1_fs), 

.dap1_sclk(dap1_sclk), 

.dap1_dout(dap1_dout), //input w.r.t CPLD 

.dap1_din(dap1_din), //output w.r.t CPLD 

//DAP2 

.dap2_fs(dap2_fs), 

.dap2_sclk(dap2_sclk), 

.dap2_dout(dap2_dout), 

.dap2_din(dap2_din), 

//DAP3 

.dap3_fs(dap3_fs), 

.dap3_sclk(dap3_sclk), 

.dap3_dout(dap3_dout), 

.dap3_din(dap3_din), 

 

.dap_route(dap_route) 

); 

 

//Actual module 

module dap_test_binary ( 

 

//DAP1 

inout reg dap1_fs, 

inout reg dap1_sclk, 

input dap1_dout, //input w.r.t CPLD 

output reg dap1_din, //output w.r.t CPLD 

//DAP2 

inout reg dap2_fs, 

inout reg dap2_sclk, 

input dap2_dout, 

output reg dap2_din, 

//DAP3 

inout reg dap3_fs, 

inout reg dap3_sclk, 

input dap3_dout, 

output reg dap3_din, 

 

input [3:0] dap_route 

); 

 

always @ (*) 

begin 

case (dap_route) 

 

4'b0000: begin //DAP1 (master) looped back to DAP2 

dap1_din = dap2_dout; 

dap2_din = dap1_dout; 

dap2_fs = dap1_fs; 

dap2_sclk = dap1_sclk; 

end  

 

4'b0001: begin //DAP2 (master) looped back to DAP1 

dap1_din = dap2_dout; 

dap2_din = dap1_dout; 

dap1_fs = dap2_fs; 

dap1_sclk = dap2_sclk; 

 

end  

 

4'b0010: begin //DAP1 (master) looped back to DAP3 

dap1_din = dap3_dout; 

dap3_din = dap1_dout; 

dap3_fs = dap1_fs; 

dap3_sclk = dap1_sclk; 

 

end  

 

4'b0011: begin //DAP3 (master) looped back to DAP1 

dap1_din = dap3_dout; 

dap3_din = dap1_dout; 

dap1_fs = dap3_fs; 

dap1_sclk = dap3_sclk; 

 

end  

 

default: begin 

dap1_fs = 1'bz; 

dap1_sclk = 1'bz; 

dap1_din = 1'bz; 

 

dap2_fs = 1'bz; 

dap2_sclk = 1'bz; 

dap2_din = 1'bz; 

 

dap3_fs = 1'bz; 

dap3_sclk = 1'bz; 

dap3_din = 1'bz; 

 

end 

 

endcase  

end  

endmodule  

 

 

//errors 

* Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(41): (vlog-2110) Illegal reference to net "dap2_fs". 

# ** Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(42): (vlog-2110) Illegal reference to net "dap2_sclk". 

# ** Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(4http://www.edaboard.com/images/smilies/icon_cool.gif : (vlog-2110) Illegal reference to net "dap1_fs". 

# ** Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(49): (vlog-2110) Illegal reference to net "dap1_sclk". 

# ** Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(56): (vlog-2110) Illegal reference to net "dap3_fs". 

# ** Error: C:/Verilog_stuff/Projects/MMSE/E1888/dap_test_binary.v(57): (vlog-2110) Illegal reference to net "dap3_sclk". 

 

 

Thanks for your help. 

 

regards 

--- Quote End ---  

 

 

 

Hi, 

 

sorry I did not saw it is Modelsim related. At least Quartus could compile the code without an error. I will test the code with modelsim now. 

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
‎12-02-2010 04:18 PM
1,379 Views

Looks like it might be an issue with my flawed implementation of bidirectional ports. Help would be appreciated. 

 

Thanks
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