Modelsim vs Xilinx

[Savageza]

I use modelsim to develop my VHDL modules and testbenches. And then create components in Xillinx (Vivado/Vitus).

I have had a couple of cases where using integer instead of (un)singed would behave differently in my testbench than on hardware (Hardware gives no timing issues). 

replace
signal sync0_ave, sync1_ave : integer := 0; 

with
signal sync0_ave, sync1_ave : unsigned(31 downto 0) := (others => '0');

and then

sync0_ave <= sync0_ave + to_integer(unsigned(reg_rdata_array(REG_VAUX0)));
sync1_ave <= sync1_ave + to_integer(unsigned(reg_rdata_array(REG_VAUX1)));

with

sync0_ave <= sync0_ave + unsigned(reg_rdata_array(REG_VAUX0));
sync1_ave <= sync1_ave + unsigned(reg_rdata_array(REG_VAUX1));

The latter would give the result expected on hardware. BOTH gives the same result in test bench.

Is there something I am missing?

[roeekalinsky]

@Savageza,

First thing you're missing is that this is a forum for Intel/Altera Quartus tool support, whereas you're targeting AMD/Xilinx, a competitor. Your question has nothing to do with Quartus.  Although really your question has little to do with Xilinx either.  It's a VHDL fundamentals question.

The second thing you're missing is that the VHDL integer type can only represent integer values from -2^31 to 2^31-1, whereas unsigned(31 downto 0) can only represent integer values from 0 to 2^32-1 (as well as metavalues). These integer value ranges are not equivalent, they only partly overlap, and the conversion you're performing between the two in the first example is not valid over the entire range of possible values. The tools should be complaining about this. I'd be surprised if they're not at least throwing a warning (which you should be paying attention to!).

Anyhow, as general practice, your use of a signal of type integer in code intended for synthesis is inappropriate. You should be using the unsigned type from the ieee.numeric_std library (or the signed type if signed values are needed), with bit range appropriately sized for whatever you're doing.